Memory device having a non-uniform redundancy decoder arrangement

Claim 2

A memory device formed with at least one memory block, each memory block having individual input/output paths and comprising: an array of memory cells arranged in rows and columns and configured in sub-blocks, each sub-block comprising a plurality of memory cells arranged in rows and sub-columns; row address circuitry for selecting a row of memory cells; column address circuitry for selecting a memory cell in a column which intersects a selected row; a plurality of redundant memory cells arranged in a plurality of redundant columns, each redundant column including a redundant sub-column for each sub-block of memory cells in the respective memory block; and address repair circuitry for addressing redundant sub-columns, said address repair circuitry comprising multiple decoders which are connected to the plurality of redundant columns nonuniformly such that more decoders are coupled to one of the redundant columns than another of the redundant columns, each of the multiple decoders programmable for selecting a redundant sub-column based on a sub-column address.

Claim 3

A memory device formed with a plurality of data blocks having individual input/output paths, a first of the data blocks comprising: an array of memory cells arranged in addressable rows and columns along row lines and column lines and configured in sub-blocks, each sub-block comprising a plurality of memory cells; a group of redundant memory cells arranged along the row and column lines of the array and forming a plurality of repair columns of memory cells; row address circuitry for selecting a row of the memory cells in said array based on row address information; column address circuitry for selecting a memory cell in a column which intersects a selected row; and a plurality of column repair decoder circuits that are connected to the plurality of repair columns and are programmable with column and row address information corresponding to a section of an array column containing a defective memory cell to replace the defective memory cell with a memory cell from one of the plurality of repair columns, a first of the plurality of repair columns connected to a different number of column repair decoder circuits than a second of the plurality of repair columns so that the distribution of column repair decoder circuits that is connected to the plurality of repair columns is nonuniform.

Claim 4

A memory device formed with a plurality of data blocks having individual input/output paths, a first of the data blocks comprising: an array of memory cells arranged in addressable rows and columns along row lines and column lines and configured in sub-blocks, each sub-block comprising a plurality of memory cells; a group of redundant memory cells arranged along the row and column lines of the array and forming a plurality of repair columns of memory cells; row address circuitry for selecting a row of the memory cells in said array based on row address information; column address circuitry for selecting a memory cell in a column which intersects a selected row; and a plurality of column repair decoder circuits that are connected to the plurality of repair columns and are programmable with column and row address information corresponding to a section of an array column containing a defective memory cell to replace the defective memory cell with a memory cell from one of the plurality of repair columns, a first of the plurality of repair columns connected to a different number of column repair decoder circuits than a second of the plurality of repair columns so that the distribution of column repair decoder circuits that is connected to the plurality of repair columns is nonuniform.

Claim 5

A memory block, comprising: a plurality of sub-blocks of memory cells arranged in rows and columns that are selectable through row address information and column address information; redundant memory cells arranged in a plurality of redundant columns; row address circuitry for selecting a row of memory cells in response to a row address; column address circuitry for selecting a column of memory cells in response to a column address; and a plurality of redundant column selection circuits coupled to the plurality of redundant columns of redundant memory cells, a first redundant column of redundant memory cells coupled to a different number of redundant column selection circuits than a second redundant column of redundant memory cells.

Claim 6

A memory block, comprising: a plurality of sub-blocks of memory cells arranged in rows and columns that are selectable through row address information and column address information; redundant memory cells arranged in a plurality of redundant columns; row address circuitry for selecting a row of memory cells in response to a row address; column address circuitry for selecting a column of memory cells in response to a column address; and a plurality of redundant column selection circuits coupled to the plurality of redundant columns of redundant memory cells, a first redundant column of redundant memory cells coupled to a different number of redundant column selection circuits than a second redundant column of redundant memory cells.

Claim 7

The memory block of claim 3 wherein the plurality of redundant column selection circuits are programmable to hold row addresses of defective memory cells within the sub-blocks of memory cells so that a column of redundant memory cells may be used to replace defective memory cells residing in more than one memory sub-block.

Claim 8

A memory device comprising: a memory array having addressable memory cells; addressable redundant columns of redundant memory cells for replacing defective memory cells in the memory array; a plurality of decoders coupled to the addressable redundant columns of redundant memory cells for decoding addresses of the defective memory cells in the memory array and for selecting addressable redundant sub-columns of redundant memory cells to replace the defective memory cells; and wherein the plurality of decoders are coupled to the addressable redundant columns of redundant memory cells nonuniformly such that some of the addressable redundant columns of redundant memory cells have more decoders coupled to them than another of the addressable redundant columns.

Claim 9

A memory device comprising: a memory array having addressable memory cells; addressable redundant columns of redundant memory cells for replacing defective memory cells in the memory array; a plurality of decoders coupled to the addressable redundant columns of redundant memory cells for decoding addresses of the defective memory cells in the memory array and for selecting addressable redundant sub-columns of redundant memory cells to replace the defective memory cells; and wherein the plurality of decoders are coupled to the addressable redundant columns of redundant memory cells nonuniformly such that some of the addressable redundant columns of redundant memory cells have more decoders coupled to them than another of the addressable redundant columns.

Claim 10

A redundancy arrangement for a random access memory device having an array of memory cells that is organized into sub-blocks of memory that contain rows and columns of the memory cells, comprising: a group of redundant memory cells organized into columns so that a defective column of memory cells of a sub-block of memory may be replaced with a redundant column of memory cells; and a plurality of redundant column decoders connected to the columns of redundant memory cells with one column of redundant memory cells connected to more redundant column decoders than another column of redundant memory cells, thereby yielding a nonuniform distribution of redundant column decoders.

Claim 11

A redundancy arrangement for a random access memory device having an array of memory cells that is organized into sub-blocks of memory that contain rows and columns of the memory cells, comprising: a group of redundant memory cells organized into columns so that a defective column of memory cells of a sub-block of memory may be replaced with a redundant column of memory cells; and a plurality of redundant column decoders connected to the columns of redundant memory cells with one column of redundant memory cells connected to more redundant column decoders than another column of redundant memory cells, thereby yielding a nonuniform distribution of redundant column decoders.

Claim 12

A memory device comprising: a memory array having addressable memory cells; addressable columns of redundant memory cells for replacing defective memory cells in the memory array; a plurality of decoders connected to the plurality of addressable columns of redundant memory cells for decoding column and at least partial row addresses of the defective memory cells in the memory array to select the addressable redundant memory cells as replacements for the defective memory cells in the memory array, the plurality of decoders being connected nonuniformly to the addressable columns of redundant memory cells so that at least one of the addressable columns of redundant memory cells is connected to more decoders than another of the addressable columns of redundant memory cells.

Claim 13

A memory device comprising: a memory array having addressable memory cells; addressable columns of redundant memory cells for replacing defective memory cells in the memory array; a plurality of decoders connected to the plurality of addressable columns of redundant memory cells for decoding column and at least partial row addresses of the defective memory cells in the memory array to select the addressable redundant memory cells as replacements for the defective memory cells in the memory array, the plurality of decoders being connected nonuniformly to the addressable columns of redundant memory cells so that at least one of the addressable columns of redundant memory cells is connected to more decoders than another of the addressable columns of redundant memory cells.

Claim 14

A memory block comprising: a plurality of sub-blocks of memory cells arranged in addressable rows and columns; redundant memory cells arranged in redundant columns; row address circuitry for selecting a row of the memory cells in response to a row address; column address circuitry for selecting a column of memory cells in response to a column address; and a plurality of redundant column selection circuits that are coupled to the redundant columns of redundant memory cells for addressing redundant sub-columns, in response to array sub-column address, the redundant column selection circuits including multiple decoders connected to the redundant columns of redundant memory cells so that at least one of the redundant columns is connected to more decoders than another of the redundant columns.

Claim 15

A memory block comprising: a plurality of sub-blocks of memory cells arranged in addressable rows and columns; redundant memory cells arranged in redundant columns; row address circuitry for selecting a row of the memory cells in response to a row address; column address circuitry for selecting a column of memory cells in response to a column address; and a plurality of redundant column selection circuits that are coupled to the redundant columns of redundant memory cells for addressing redundant sub-columns, in response to array sub-column address, the redundant column selection circuits including multiple decoders connected to the redundant columns of redundant memory cells so that at least one of the redundant columns is connected to more decoders than another of the redundant columns.