US5270655A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit having light emitting devices
Assignee: Panasonic Holdings Corp
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Filing: 1991-10-01
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Granted: 1993-12-14
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Expires: 2011-10-01
Abstract
Abstract The light emitting device has a series circuit comprised of a MOS transistor and a P + N + junction. When a voltage greater than the breakdown voltage of the P + N + junction is applied to this series circuit, as well as putting the MOS transistor into a conductive state, the P + N + junction breaks down allowing a breakdown current to flow, and weak light is generated from the P + N + junction. Since this light emitting device can be produced in nearly the same size as an MOS transistor, using a conventional CMOS technique, it can be integrated into a chip with a high integration level, and the integration of the light emitting device causes almost no drop in the integration level. When this light emitting device is integrated in a semiconductor integrated circuit, the state of the circuit can be easily monitored by observing the light pattern of the device.
Inventors
- 👤 Yasuhiro Tomita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:10
CPC Classifications
H; H10; H10H; H10H29/00; H10H29/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
163 words
A test apparatus for testing a semiconductor integrated circuit in which at least one light emitting device is integrated, comprising: a pattern generator for generating and transmitting a plurality of test pattern signals to said integrated circuit to cause said light emitting device to produce an emission/non-emission light pattern that indicates internal state of said integrated circuit; optical means, including an output terminal, for receiving light emitted from said light emitting device, for generating a further plurality of electric signals which indicate light emission from said light emitting device, and for selectively transmitting at least one of said further plurality of electric signals to said optical means output terminal said pattern generator including signal generation means for generating a timing signal and for transmitting said timing signal to said optical means to selectively enable one or more functions of said optical means so that at least one of said further plurality of electric signals is selectively transmitted to said optical means output terminal.
Claim 2
Dependent Claim
163 words
A test apparatus for testing a semiconductor integrated circuit in which at least one light emitting device is integrated, comprising: a pattern generator for generating and transmitting a plurality of test pattern signals to said integrated circuit to cause said light emitting device to produce an emission/non-emission light pattern that indicates internal state of said integrated circuit; optical means, including an output terminal, for receiving light emitted from said light emitting device, for generating a further plurality of electric signals which indicate light emission from said light emitting device, and for selectively transmitting at least one of said further plurality of electric signals to said optical means output terminal said pattern generator including signal generation means for generating a timing signal and for transmitting said timing signal to said optical means to selectively enable one or more functions of said optical means so that at least one of said further plurality of electric signals is selectively transmitted to said optical means output terminal.
Claim 3
Dependent Claim
21 words
The test apparatus according to claim 1 wherein said timing signal is determined depending on said plurality of test pattern signals.
Claim 4
Dependent Claim
42 words
The test apparatus according to claim 2 wherein said integrated circuit comprises a plurality of said integrated light emitting devices, said device producing a light pattern in response to outputs from the integrated circuit to indicate internal states of said integrated circuit.
Claim 5
Dependent Claim
35 words
The test apparatus according to claim 1, wherein detection of said at least one of said further plurality of electric signals at said optical means output terminal indicates correct operation of said semiconductor integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |