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US5269012A
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Stack memory system including an address buffer for generating a changed address by inverting an address bit
Assignee: Panasonic Holdings Corp
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Filing: 1990-11-28
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Granted: 1993-12-07
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Expires: 2010-11-28
Abstract
Abstract A stack memory includes an address input section, a memory element array, a stack pointer, and an address buffer. The address input section has "n" bits where "n" denotes a predetermined number. The memory element array has 2 n words and is connected to the address input section. The stack pointer generates a first address signal having "n" bits, and an n-th bit of the first address signal is inverted by a control signal. The address buffer is connected between the stack pointer and the address input section. The address buffer generates a second address signal from the first address signal and outputs the second address signal to the address input section. The second address signal remains equal to the first address signal in bits except an n-th bit, and the n-th bit of the first address signal is inverted again by the control signal to be converted into the n-th bit of the second address signal.
Inventors
- 👤 Masaitsu Nakajima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
161 words
A stack memory comprising: an address input section having "n" bits where "n" denotes a predetermined number; a memory element array having 2 n words and being connected to the address input section; a stack pointer generating a first n bit address signal having "n" bits, wherein an n-th bit of the first address signal is inverted in response to a control signal; and an address buffer connected between the stack pointer and the address input section, the address buffer generating a second address signal of n bits from the first address signal and outputting the second address signal to the address input section, wherein bit values of the bits of the second address signal are equal to bit values of the bits of the first address signal except for an n-th bit, the n-th bit of the first address signal being inverted again in response to the control signal and supplied as the n-th bit of the second address signal.
Claim 2
Dependent Claim
161 words
A stack memory comprising: an address input section having "n" bits where "n" denotes a predetermined number; a memory element array having 2 n words and being connected to the address input section; a stack pointer generating a first n bit address signal having "n" bits, wherein an n-th bit of the first address signal is inverted in response to a control signal; and an address buffer connected between the stack pointer and the address input section, the address buffer generating a second address signal of n bits from the first address signal and outputting the second address signal to the address input section, wherein bit values of the bits of the second address signal are equal to bit values of the bits of the first address signal except for an n-th bit, the n-th bit of the first address signal being inverted again in response to the control signal and supplied as the n-th bit of the second address signal.
Claim 3
Dependent Claim
133 words
A stack memory comprising: a memory element array having a plurality of words; means for generating a first address signal; means for generating a second address signal from the first address signal; means for accessing one of the words of the memory element array in response to the second address signal; means for changing the first address signal in response to a control signal; and means responsive to the control signal for providing the second address signal corresponding to an unchanged first address signal by compensating for the changing of the first address signal by the means for changing the first address signals, operation of said means for providing the second address signal being independent of any change in the first address signal effected by said means for changing the first address signal.
Claim 4
Dependent Claim
133 words
A stack memory comprising: a memory element array having a plurality of words; means for generating a first address signal; means for generating a second address signal from the first address signal; means for accessing one of the words of the memory element array in response to the second address signal; means for changing the first address signal in response to a control signal; and means responsive to the control signal for providing the second address signal corresponding to an unchanged first address signal by compensating for the changing of the first address signal by the means for changing the first address signals, operation of said means for providing the second address signal being independent of any change in the first address signal effected by said means for changing the first address signal.
Claim 5
Dependent Claim
158 words
A stack memory comprising: a memory element array having a plurality of words; means for generating a first address signal; means for generating a second address signal from the first address signal; means for allowing an access to one of the words of the memory element array in response to the second address signal; means for equalizing the first address signal and the second address signal in the absence of an active control signal; means for changing the first address signal in response to the active control signal; and means responsive to the active control signal for providing the second address signal corresponding to an unchanged first address signal by compensating for the changing of the first address signal by the means for changing the first address signal, operation of said means for providing the second address signal being independent of any change in the first address signal effected by said means for changing the first address signal.
Claim 6
Dependent Claim
158 words
A stack memory comprising: a memory element array having a plurality of words; means for generating a first address signal; means for generating a second address signal from the first address signal; means for allowing an access to one of the words of the memory element array in response to the second address signal; means for equalizing the first address signal and the second address signal in the absence of an active control signal; means for changing the first address signal in response to the active control signal; and means responsive to the active control signal for providing the second address signal corresponding to an unchanged first address signal by compensating for the changing of the first address signal by the means for changing the first address signal, operation of said means for providing the second address signal being independent of any change in the first address signal effected by said means for changing the first address signal.
Claim 7
Dependent Claim
73 words
The stack memory of claim 3 wherein the changing means comprises means for inverting a value of a highest bit of the first address signal in response to the active control signal, and wherein the means for providing the second address signal corresponding to an unchanged first address signal comprises means for inverting again the inverted value of said highest bit of the first address signal in response to the active control signal.
Claim 8
Dependent Claim
96 words
A stack memory comprising: a memory responsive to an n-bit address signal for accessing memory cells of said memory; stack pointer means for supplying an n-bit stack pointer signal and including means for selectively inverting one bit in response to a control signal; and address buffer means for receiving said n-bit stack pointer signal and, in response to said control signal, for selectively inverting the inverted said one bit of said n-bit stack pointer signal to make said n-bit stack pointer signal into said n-bit address signal and supplying said n-bit address signal to said memory.
Claim 9
Dependent Claim
96 words
A stack memory comprising: a memory responsive to an n-bit address signal for accessing memory cells of said memory; stack pointer means for supplying an n-bit stack pointer signal and including means for selectively inverting one bit in response to a control signal; and address buffer means for receiving said n-bit stack pointer signal and, in response to said control signal, for selectively inverting the inverted said one bit of said n-bit stack pointer signal to make said n-bit stack pointer signal into said n-bit address signal and supplying said n-bit address signal to said memory.
Claim 10
Dependent Claim
103 words
The stack memory according to claim 5, wherein said means for selectively inverting one bit includes a first exclusive NOR gate means receiving said control signal and said one bit, and said address means for selectively inverting the inverted said one bit includes non-inverting means for not inverting the other bits of the n-bit stack pointer signal and a second exclusive NOR gate means receiving said control signal and the inverted said one bit for selectively inverting said one bit responsive to said control signal, said non-inverting means and said second exclusive NOR gate means supplying said n-bit address signal to said memory.
Claim 11
Dependent Claim
113 words
A stack memory comprising: a memory including a plurality of memory cells, said memory responsive to a memory address signal for accessing said memory cells; stack pointer means for supplying an n-bit stack pointer address signal; and address buffer means responsive to a control signal for selectively inverting one bit of said stack pointer address signal to make said stack pointer address signal into said memory address signal, and for supplying said memory address signal to said memory whereby said n-bits of said memory address signal selectively correspond to (i) said stack pointer address signal with no bit values inverted, or (ii) said stack pointer address signal with only one bit value inverted.
Claim 12
Dependent Claim
113 words
A stack memory comprising: a memory including a plurality of memory cells, said memory responsive to a memory address signal for accessing said memory cells; stack pointer means for supplying an n-bit stack pointer address signal; and address buffer means responsive to a control signal for selectively inverting one bit of said stack pointer address signal to make said stack pointer address signal into said memory address signal, and for supplying said memory address signal to said memory whereby said n-bits of said memory address signal selectively correspond to (i) said stack pointer address signal with no bit values inverted, or (ii) said stack pointer address signal with only one bit value inverted.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |