RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register

Claim 2

A data processor, employing a reduced instruction set computer architecture, the instruction code length of which is fixed to a predetermined bit length, comprising: an instruction fetch unit for fetching from a memory a first and a second instruction each having said predetermined bit length, and for outputting the first and second instructions in parallel; a first instruction decoder for decoding the first instruction received from said instruction fetch unit; a second instruction decoder for decoding the second instruction received from said instruction fetch unit; an instruction execution unit, including at least an arithmetic and logic unit, a shifter and a register file of a plurality of registers, being controlled by either one of a decoded results from said first instruction decoder and a decoded result from said second instruction decoder; a first comparator for comparing first inputs comprising a destination field of the first instruction outputted from said instruction fetch unit and a first source field of the second instruction outputted from said instruction fetch unit; a second comparator for comparing second inputs comprising the destination field of the first instruction outputted from said instruction fetch unit and a destination field of the second instruction outputted from said instruction fetch unit; a signal transmission path for supplying an output of said shifter directly to an input of said arithmetic and logic unit when said first instruction outputted from said instruction fetch unit is a first immediate instruction which instructs said shifter to operate on a first immediate data, when said second instruction outputted from said instruction fetch unit is a second immediate instruction which instructs said arithmetic and logic unit to operate on a second immediate data, and when both of said first and second comparators indicate the first and second inputs are equal, wherein a result of said shift operation of said shifter operating on said first immediate data of said first immediate instruction is supplied to said input of said arithmetic logic unit through said signal transmission path, and said result of said operation of said arithmetic logic unit operating on said second immediate data of said second immediate instruction is stored in a designated register in said register file thereby executing said first and second immediate instructions simultaneously within one clock cycle using said arithmetic and logic unit, said shifter and said register file.

Claim 3

A data processor according to claim 1, wherein said first immediate instruction is a load upper immediate instruction which shifts said first immediate data left by a predetermined bit number using said shifter, and wherein said second immediate instruction is an immediate instruction which operates on information read from one register in said register field designated by said first source field of the second immediate instruction and a data related to said second immediate data using said arithmetic and logic unit and stores a result of said logical operation into one register in said register file.

Claim 4

A data processor according to claim 2, wherein said second immediate instruction is an OR immediate instruction which computes an OR operation between said information read from said one register and said data related to said second immediate data.

Claim 5

A data processor, employing a reduced instruction set computer architecture the instruction code length of which is fixed to a predetermined bit length, comprising: an instruction fetch unit for fetching therein from a memory first and second instructions each having said predetermined bit length and for outputting therefrom the first and second instructions in parallel; a first instruction decoder for receiving as an input thereto an operation code of the first instruction supplied from said instruction fetch unit; a second instruction decoder for receiving as an input thereto an operation code of the second instruction supplied from said instruction fetch unit; an instruction execution unit, including at least an arithmetic and logic unit; a shifter and a register file of a plurality of registers, being controlled by either one of a decoded result from said first instruction decoder and a decoded result from said second instruction decoder; a first comparator for comparing information of a destination field of the first instruction outputted from said instruction fetch unit with information of a first source field of the second instruction outputted from said instruction fetch unit; a second comparator for comparing said information of said destination field of the first instruction outputted from said instruction fetch unit with information of a destination field of the second instruction outputted from said instruction fetch unit; a signal transmission path for supplying an output of said shifter to an input of said arithmetic and logic unit so as to bypass said register field and for non-supplying said output of said shifter to said register file under condition that said first instruction outputted from said instruction fetch unit is a first immediate instruction which uses not said arithmetic and logic unit but said shifter in connection with an immediate data thereof and ordinarily stores a result of a shift operation of said shifter in connection with said immediate data of said first immediate instruction into one register of said register file designation by said destination field of said first immediate instruction, said second instruction outputted from said instruction fetch unit is a second immediate instruction which uses not said shifter but said arithmetic and logic unit in connection with an immediate data thereof and ordinarily stores a result of an operation of said arithmetic and logic unit in connection with said immediate data of said second immediate instruction into one register of said register file designated by said destination field of said second immediate instruction, said first immediate instruction and said second immediate instruction are outputted in parallel from said instruction fetch unit, and each of said first and second comparators detects that comparing inputs thereof are equal to each other, wherein under said condition said result of said shift operation of said shifter in connection with said immediate data of said first immediate instruction is supplied not to said designated register in said register file but to said input of said arithmetic and logic unit through said signal transmission path, and said result of said operation of said arithmetic and logic unit in connection with said immediate data of said second immediate instruction is stored in said designated register in said register field so as to execute said first and second immediate instruction simultaneously within one clock cycle by using said arithmetic and logic unit, said shifter and said register field.

Claim 6

A data processor, employing a reduced instruction set computer architecture the instruction code length of which is fixed to a predetermined bit length, comprising: an instruction fetch unit for fetching therein from a memory first and second instructions each having said predetermined bit length and for outputting therefrom the first and second instructions in parallel; a first instruction decoder for receiving as an input thereto an operation code of the first instruction supplied from said instruction fetch unit; a second instruction decoder for receiving as an input thereto an operation code of the second instruction supplied from said instruction fetch unit; an instruction execution unit, including at least an arithmetic and logic unit; a shifter and a register file of a plurality of registers, being controlled by either one of a decoded result from said first instruction decoder and a decoded result from said second instruction decoder; a first comparator for comparing information of a destination field of the first instruction outputted from said instruction fetch unit with information of a first source field of the second instruction outputted from said instruction fetch unit; a second comparator for comparing said information of said destination field of the first instruction outputted from said instruction fetch unit with information of a destination field of the second instruction outputted from said instruction fetch unit; a signal transmission path for supplying an output of said shifter to an input of said arithmetic and logic unit so as to bypass said register field and for non-supplying said output of said shifter to said register file under condition that said first instruction outputted from said instruction fetch unit is a first immediate instruction which uses not said arithmetic and logic unit but said shifter in connection with an immediate data thereof and ordinarily stores a result of a shift operation of said shifter in connection with said immediate data of said first immediate instruction into one register of said register file designation by said destination field of said first immediate instruction, said second instruction outputted from said instruction fetch unit is a second immediate instruction which uses not said shifter but said arithmetic and logic unit in connection with an immediate data thereof and ordinarily stores a result of an operation of said arithmetic and logic unit in connection with said immediate data of said second immediate instruction into one register of said register file designated by said destination field of said second immediate instruction, said first immediate instruction and said second immediate instruction are outputted in parallel from said instruction fetch unit, and each of said first and second comparators detects that comparing inputs thereof are equal to each other, wherein under said condition said result of said shift operation of said shifter in connection with said immediate data of said first immediate instruction is supplied not to said designated register in said register file but to said input of said arithmetic and logic unit through said signal transmission path, and said result of said operation of said arithmetic and logic unit in connection with said immediate data of said second immediate instruction is stored in said designated register in said register field so as to execute said first and second immediate instruction simultaneously within one clock cycle by using said arithmetic and logic unit, said shifter and said register field.

Claim 7

A data processor according to claim 4, wherein said first immediate instruction is a load upper immediate instruction which shifts said immediate data thereof to the left-hand side by a predetermined bit number by using said shifter and ordinarily stores the shift result from said shifter into one register of said register field designated by said destination field thereof, and wherein said second immediate instruction is an immediate instruction which ordinarily reads out information from one register in said register file designated by said first source field thereof, ordinarily carries out a logical operation of the information read out from said one register in said register file designated by said first source field thereof and a data related to said immediate data thereof by using said arithmetic and logic unit and stores a result of said logical operation into one register in said register file designated by said destination field thereof.

Claim 8

A data processor according to claim 5, wherein said second immediate instruction is an or immediate instruction which computes an OR operation between said information read out from said one register and said data related to said immediate data thereof.