US5269005A — Method and apparatus for transferring data within…

Claim 1

Independent Claim 206 words

A processing system comprising: an independently arbitrated system bus; a processor coupled to said system bus; system memory coupled to said system bus; an interrupt controller coupled to said system bus; an independently arbitrated first I/O bus coupled to said system bus, said first I/O bus hosting a resident agent thereon as a resource for said processing system; and first I/O bus interface means for coupling said first I/O bus to said system bus, said I/O bus interface means comprising buffering means for latching a block of data to be written from said agent to said system memory and controller means for controlling said buffering means and issuing a retry signal on said system bus in response to an interrupt acknowledge generated by said processor if said buffering means contains any portion of the block of data to be written to said system memory thereby deferring acting upon said interrupt acknowledge until all of the block of data latched in said buffering means has been written to system memory, wherein said agent is able to cause an interrupt signal to be delivered to said processor so that said processor generates the interrupt acknowledge before all of the block of data is written to said main memory.

Claim 2

Dependent Claim 206 words

A processing system comprising: an independently arbitrated system bus; a processor coupled to said system bus; system memory coupled to said system bus; an interrupt controller coupled to said system bus; an independently arbitrated first I/O bus coupled to said system bus, said first I/O bus hosting a resident agent thereon as a resource for said processing system; and first I/O bus interface means for coupling said first I/O bus to said system bus, said I/O bus interface means comprising buffering means for latching a block of data to be written from said agent to said system memory and controller means for controlling said buffering means and issuing a retry signal on said system bus in response to an interrupt acknowledge generated by said processor if said buffering means contains any portion of the block of data to be written to said system memory thereby deferring acting upon said interrupt acknowledge until all of the block of data latched in said buffering means has been written to system memory, wherein said agent is able to cause an interrupt signal to be delivered to said processor so that said processor generates the interrupt acknowledge before all of the block of data is written to said main memory.

Claim 3

Dependent Claim 98 words

A processing system as claimed in claim 1 further comprising at least one independently arbitrated additional I/O bus coupled to said system bus, said additional I/O bus hosting resident agents thereon as resources for said processing system; and at least one additional I/O bus interface means for coupling said additional I/O bus to said system bus, said additional I/O bus interface means comprising buffering means for latching data to be written from the agents on said additional I/O bus to said system memory and controller means for controlling said buffering means of said additional I/O bus interface means.

Claim 4

Dependent Claim 47 words

A processing system as claimed in claim 1 wherein said interrupt controller monitors said system bus and issues an interrupt vector in response to the interrupt acknowledge if the retry signal is not issued by said first I/O bus interface means within a predetermined period of time.

Claim 5

Dependent Claim 258 words

A processor system comprising: at least one independently arbitrated system bus; a processor coupled to each system bus; system memory coupled to each system bus; an interrupt controller coupled to said system bus; multiple independently arbitrated I/O buses coupled to said system bus, each of said I/O buses hosting a resident agent thereon as a resource for said processing system and comprising a primary I/O bus; and I/O bus interface means for coupling said I/O buses to said system bus, said I/O bus interface means comprising buffering means for latching data to be written from each of said agents on said I/O buses to said system memory and controller means for controlling said buffering means, a portion of said I/O bus interface means associated with said primary I/O bus further providing for issuing a retry signal on said system bus in response to an interrupt acknowledge generated by said processor if the buffering means associated with said portion of said I/O bus interface means contains latched data to be written to said system memory thereby deferring acting upon said interrupt acknowledge until all data latched in the buffering means associated with said portion of said I/O bus interface means has been written to system memory, wherein the agent hosted on said primary I/O bus is able to cause an interrupt signal to be delivered to said processor so that said processor generates the interrupt acknowledge before all data latched in the buffering means associated with said portion of said I/O bus interface means is written to system memory.

Claim 6

Dependent Claim 258 words

A processor system comprising: at least one independently arbitrated system bus; a processor coupled to each system bus; system memory coupled to each system bus; an interrupt controller coupled to said system bus; multiple independently arbitrated I/O buses coupled to said system bus, each of said I/O buses hosting a resident agent thereon as a resource for said processing system and comprising a primary I/O bus; and I/O bus interface means for coupling said I/O buses to said system bus, said I/O bus interface means comprising buffering means for latching data to be written from each of said agents on said I/O buses to said system memory and controller means for controlling said buffering means, a portion of said I/O bus interface means associated with said primary I/O bus further providing for issuing a retry signal on said system bus in response to an interrupt acknowledge generated by said processor if the buffering means associated with said portion of said I/O bus interface means contains latched data to be written to said system memory thereby deferring acting upon said interrupt acknowledge until all data latched in the buffering means associated with said portion of said I/O bus interface means has been written to system memory, wherein the agent hosted on said primary I/O bus is able to cause an interrupt signal to be delivered to said processor so that said processor generates the interrupt acknowledge before all data latched in the buffering means associated with said portion of said I/O bus interface means is written to system memory.

Claim 7

Dependent Claim 49 words

A processing system as claimed in claim 4 wherein said interrupt controller monitors said system bus and issues an interrupt vector in response to the interrupt acknowledge if the retry signal is not issued by said portion of said I/O bus interface means within a predetermined period of time.

Claim 8

Independent Claim 200 words

A method of operating a processor system comprising the steps of: interconnecting a processor to a system bus; interconnecting system memory to said system bus; interfacing a first I/O bus to said system bus by means of first I/O bus interface means; coupling a first agent to said first I/O bus such that said first I/O bus can connect said first agent to said processor, and to said system memory; independently arbitrating access to said system bus and said first I/O bus; packing data to be written into said system memory from said first agent coupled to said first I/O bus, said data being packed into said first I/O bus interface means; generating an interrupt signal by said first agent so as to cause said processor to generate an interrupt acknowledge upon a write operation performed by said first agent to said system memory but before data to be written from said first agent to said system memory is received by said system memory; and deferring acting upon said interrupt acknowledge, said deferring step being initiated in response to detection of the interrupt acknowledge generated by the processor when packed data is present in said first I/O bus interface means.

Claim 9

Independent Claim 200 words

A method of operating a processor system comprising the steps of: interconnecting a processor to a system bus; interconnecting system memory to said system bus; interfacing a first I/O bus to said system bus by means of first I/O bus interface means; coupling a first agent to said first I/O bus such that said first I/O bus can connect said first agent to said processor, and to said system memory; independently arbitrating access to said system bus and said first I/O bus; packing data to be written into said system memory from said first agent coupled to said first I/O bus, said data being packed into said first I/O bus interface means; generating an interrupt signal by said first agent so as to cause said processor to generate an interrupt acknowledge upon a write operation performed by said first agent to said system memory but before data to be written from said first agent to said system memory is received by said system memory; and deferring acting upon said interrupt acknowledge, said deferring step being initiated in response to detection of the interrupt acknowledge generated by the processor when packed data is present in said first I/O bus interface means.

Claim 10

Dependent Claim 101 words

A method of operating a processor system as claimed in claim 6 further comprising the steps of: interfacing a second I/O bus by means of second I/O bus interface means to said system bus; coupling second agents to said second I/O bus such that said second I/O bus can connect said second agents to one another, to said processor, and to said system memory; independently arbitrating access to said second I/O bus; and packing data to be written into said system memory from agents coupled to said second I/O bus, said data being packed into said second I/O bus interface means.

Claim 11

Dependent Claim 49 words

A method of operating a processor system as claimed in claim 7 further comprising the step of pre-fetching data to be read from said system memory to agents coupled to said first and second I/O buses, said data being prefetched into said first and second I/O bus interface means.

Claim 12

Dependent Claim 106 words

A method of operating a processor system as claimed in claim 7 wherein said deferring step comprises the steps of: generating an interrupt acknowledge in response to said interrupt signal, said interrupt acknowledge being generated by said processor; receiving said interrupt acknowledge in said first I/O bus interface means which serves said first I/O bus to which said first agent is coupled; determining whether packed data in said first I/O bus interface means has been transferred to said system memory; and generating a retry signal for said processor if packed data in said first I/O bus interface means has not been transferred to said system memory.

Claim 13

Dependent Claim 56 words

A method of operating a processor system as claimed in claim 9 wherein said deferring step further comprises the steps of: monitoring said system bus for a predetermined period of time to determine whether the retry signal is generated; and generating an interrupt vector if the retry signal is not received within said predetermined time period.

Claim 14

Dependent Claim 65 words

A method of operating a processor system as claimed in claim 9 wherein said deferring step further comprises the steps of: removing said processor which generated said interrupt acknowledge from said system bus; and denying access to said system bus by said processor which generated said interrupt acknowledge until packed data in said first I/O bus interface means has been transferred to said system memory.

Claim 15

Dependent Claim 75 words

A method of operating a processor system as claimed in claim 11 wherein the step of denying access to said system bus by said processor which generated said interrupt acknowledge until packed data in said first I/O bus interface means has been transferred to said system memory comprises the step of generating an I/O bus busy signal until all packed data in said first I/O bus interface means has been transferred to said system memory.

Claim 16

Dependent Claim 76 words

A method of operating a processor system as claimed in claim 12 further comprising the step of locking the first I/O bus after terminating the step of generating an I/O bus busy signal as a result of transferring all packed data from said first I/O bus interface means to said system memory to prevent another agent from gaining control of the first I/O bus until the interrupt acknowledge operations have been completed for the interrupt signal.

Claim 17

Dependent Claim 49 words

A method of operating a processor system as claimed in claim 12 wherein the step of generating an I/O bus busy signal until all packed data has been transferred from said first I/O bus interface means to said system memory is performed by said first I/O bus interface means.

Claim 18

Dependent Claim 50 words

A method of operating a processor system as claimed in claim 14 wherein said processor includes a cache memory and the step of generating an I/O bus busy signal is continued until all associated coherency operations are completed for the packed data which has been transferred to said system memory.

Claim 19

Dependent Claim 51 words

A method of operating a processor system as claimed in claim 14 wherein said first I/O bus interface means issues retry signals to any processor attempting to access said first I/O bus or to do an interrupt acknowledge cycle until said first I/O bus busy signal is no longer being generated.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-12-06	1997-06-07	1997-12-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-12-06	2001-06-07	2001-12-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-12-06	2005-06-07	2005-12-07	$7700.00	Window Closed / Lapsed

Method and apparatus for transferring data within a computer system

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