Reading circuit for semiconductor memory

Claim 1

A reading circuit for a semiconductor memory in which, nearly concurrently with start of an operation of precharging a bit line pair to a first voltage supply source, clamping of said bit line pair is released while said bit line pair is connected to an input portion of a differential amplifier, said reading circuit comprising: equalizing means comprising of first, second and third switch means, wherein said first and second switch means are interposed to connect said first voltage supply source to said bit line pair respectively, and said third switch means is connected across said bit line pair for short-circuiting said bit line pair; clamping means comprising of fourth and fifth switch means which are interposed for connecting said bit line pair to said first voltage supply source respectively; and sixth and seventh switch means for connecting said bit line pair to the input portion of said differential amplifier, wherein said equalizing means is controlled by a first control line, and said clamping means is controlled by a second control line, and said sixth and seventh switch means are controlled by a third control line, and wherein said first control line turns on said equalizing means during a period of a first pulse width (ATD) fed via said first control line, and said third control line turns on said sixth and seventh switch means nearly concurrently when said equalizing means are turned on, and said third control line turns off the same after an elapse of a specified period, and said second control line turns on said clamping means for a period nearly equal to the duration during which said sixth and seventh switch means are held off.