Patent US5268873A successfully refreshed from Google Patents.
US5268873A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory apparatus
Assignee: Micron Memory Japan Ltd
•
Filing: 1992-02-14
•
Granted: 1993-12-07
•
Expires: 2012-02-14
Abstract
Abstract A ROM apparatus includes a control circuit for controlling an output buffer to be turned into a high impedance state or an off state for a predetermined time in response to a change of an address signal. For this control circuit, a supply of data read from a wrong address of a memory to an external circuit is prohibited for a duration of a false malfunction which is caused by a precharge of digit lines.
Inventors
- 👤 Kouichi Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:56
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
147 words
A semiconductor memory apparatus comprising: a memory having memory cells arranged in a matrix pattern; means for addressing said memory in accordance with a given address signal; a sense amplifier for amplifying data read from said memory subsequently to a precharge of digit lines; buffer means for supplying said data to an external circuit; means for detecting a change of said given address signal to generate an address change signal; and means for controlling said buffer means to prohibit a supply of said data to said external circuit for a predetermined time in response to said address change signal, wherein said controlling means comprises a circuit for generating a prohibiting signal having a width of said predetermined time in response to said address change signal; and an output enabling buffer circuit for turning said buffer means into a high impedance state in response to said prohibiting signal.
Claim 2
Dependent Claim
147 words
A semiconductor memory apparatus comprising: a memory having memory cells arranged in a matrix pattern; means for addressing said memory in accordance with a given address signal; a sense amplifier for amplifying data read from said memory subsequently to a precharge of digit lines; buffer means for supplying said data to an external circuit; means for detecting a change of said given address signal to generate an address change signal; and means for controlling said buffer means to prohibit a supply of said data to said external circuit for a predetermined time in response to said address change signal, wherein said controlling means comprises a circuit for generating a prohibiting signal having a width of said predetermined time in response to said address change signal; and an output enabling buffer circuit for turning said buffer means into a high impedance state in response to said prohibiting signal.
Claim 3
Dependent Claim
146 words
A semiconductor memory apparatus, comprising: a memory having memory cells arranged in a matrix pattern; means for addressing said memory in accordance with a given address signal; a sense amplifier for amplifying data read from said memory subsequently to a precharge of digit lines; buffer means for supplying said data to an external circuit; means for detecting a change of said given address signal to generate an address change signal; and means for controlling said buffer means to prohibit a supply of said data to said external circuit for a predetermined time in response to said address change signal; wherein said controlling means comprises a circuit for generating a prohibiting signal having a width of said predetermined time in response to said address change signal; and an output enabling buffer circuit for turning said buffer means into an off state in response to said prohibiting signal.
Claim 4
Dependent Claim
146 words
A semiconductor memory apparatus, comprising: a memory having memory cells arranged in a matrix pattern; means for addressing said memory in accordance with a given address signal; a sense amplifier for amplifying data read from said memory subsequently to a precharge of digit lines; buffer means for supplying said data to an external circuit; means for detecting a change of said given address signal to generate an address change signal; and means for controlling said buffer means to prohibit a supply of said data to said external circuit for a predetermined time in response to said address change signal; wherein said controlling means comprises a circuit for generating a prohibiting signal having a width of said predetermined time in response to said address change signal; and an output enabling buffer circuit for turning said buffer means into an off state in response to said prohibiting signal.
References Cited (Backward Citations)
US4982366A
Cited
US4537147A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |