Memory having a write enable controlled word line

Claim 2

An asynchronous integrated circuit memory having a write cycle, indicated by a write enable signal being in a first logic state, for writing data into the memory, and a read cycle, indicated by the write enable signal being in a second logic state, for reading data from the memory, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a word line and to a bit line pair for receiving data from the bit line pair to which it is coupled, when the word line to which it is coupled is enabled; row decoding means for receiving a row address signal and for selecting one of said word lines in response to said row address signal; bit line equalization means, coupled to the bit line pairs, for equalizing the voltages on the bit line pairs at the termination of the write cycle; and preventing means, coupled to said row decoding means, for preventing said row decoding means from selecting a different one of said word lines until said write enable signal changes from said first logic state to said second logic state, ensuring that said bit line equalization means equalizes the voltages on the bit line pairs before said different one of said word lines is selected.

Claim 3

The memory of claim 1, wherein said row decoding means further comprises: a row address predecoder having an input for receiving said row address signal and having an output for providing a predecoded row address signal; and a row selector coupled to said row address predecoder for receiving said predecoded row address signal, for performing a word line selection, and for changing such word line selection in response to a change in said row address signal.

Claim 4

The memory of claim 1, further comprising control means for providing a first control signal to said preventing means and for making said first control signal active a first predetermined delay after said write enable signal transitions from said second logic state to said first logic state, said control means making said first control signal inactive after a second predetermined delay, said second predetermined delay being less than said first predetermined delay.

Claim 5

The memory of claim 3, wherein said preventing means is further characterized as preventing said row decoding means from selecting a different one of said word lines in response to said first control signal being active.

Claim 6

The memory of claim 2, wherein said preventing means is coupled between said output of said row address predecoder and said row selector, and prevents said predecoder row address signal from being received by said row selector in response to receiving a first control signal.

Claim 7

The memory of claim 2, wherein said row address predecoder comprises a NAND logic gate having a plurality of input terminals for receiving a plurality of said row address signals and an output terminal for providing said precoded row address signal as a logical NAND of said plurality of said row address signals.

Claim 8

The memory of claim 5, wherein said preventing means comprises: a transfer gate coupled to said output of said row address predecoder, for receiving said first control signal, and for preventing said row address predecoder from providing a new predecoded row address signal to said row selector when said first control signal is active; and a latch for retaining said predecoded row address signal until a new predecoded row address signal is provided by said row address predecoder.

Claim 9

The memory of claim 7, wherein said transfer gate comprises: a P-channel transistor having a first current electrode coupled to said output of said row address predecoder, a second current electrode coupled to said row selector, and a control electrode for receiving said first control signal; an inverter having an input terminal for receiving said first control signal and an output terminal; and an N-channel transistor having a first current electrode coupled to said output of said row address predecoder, a second current electrode coupled to said row selector, and a control electrode coupled to said output of said inverter.

Claim 10

An integrated circuit memory having a write cycle, indicated by a write enable signal being in a first logic state, for writing data into the memory, and a read cycle, indicated by the write enable signal being a second logic state, for reading data from the memory, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a word line and to a bit line pair, for receiving data from the bit line pair to which it is coupled, when the word line to which it is coupled is enabled; a row address predecoder for receiving a row address signal and in response providing predecoded row address signals; a row selector coupled to said row address predecoder for receiving said predecoded row address signals, for performing a word line selection, and for changing such word line selection in response to a change in said row address signal; bit line equalization means, coupled to the bit line pairs, for equalizing the voltages on the bit line pairs at the termination of the write cycle; decoupling means, for decoupling said row address predecoder from said row selector when said write enable signal is in said first logic state; and latching means, for retaining said word line section until after said write enable signal switches to said second logic state.

Claim 11

An integrated circuit memory having a write cycle, indicated by a write enable signal being in a first logic state, for writing data into the memory, and a read cycle, indicated by the write enable signal being a second logic state, for reading data from the memory, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a word line and to a bit line pair, for receiving data from the bit line pair to which it is coupled, when the word line to which it is coupled is enabled; a row address predecoder for receiving a row address signal and in response providing predecoded row address signals; a row selector coupled to said row address predecoder for receiving said predecoded row address signals, for performing a word line selection, and for changing such word line selection in response to a change in said row address signal; bit line equalization means, coupled to the bit line pairs, for equalizing the voltages on the bit line pairs at the termination of the write cycle; decoupling means, for decoupling said row address predecoder from said row selector when said write enable signal is in said first logic state; and latching means, for retaining said word line section until after said write enable signal switches to said second logic state.

Claim 12

The memory of claim 9, wherein said row address predecoder comprises a NAND logic state having a plurality of input terminals for receiving a plurality of said row address signals and an output terminal for providing a predecoded row address signal as a logical NAND of said plurality of row address signals.

Claim 13

The memory of claim 9, further comprising control means for making a first control signal active a first predetermined delay after said write enable signal transitions from said second logic state to said first logic state, said control means making said first control signal inactive after a second predetermined delay, said second predetermined delay being less than said first predetermined delay.

Claim 14

The memory of claim 11, wherein said decoupling means is further characterized as decoupling said row address predecoder from said row selector in response to said first control signal being active.

Claim 15

The memory of claim 12, wherein said latching means comprises a latch for retaining said predecoded row address signal until a new predecoded row address signal is provided by said row decoder.

Claim 16

The memory of claim 12, wherein said decoupling means comprises: a first transistor having a first current electrode coupled to said output of said row address predecoder, a second current electrode coupled to said row selector, and a control electrode for receiving said first control signal; an inverter having an input terminal for receiving said first control signal and an output terminal; and a second transistor having a first current electrode coupled to said output of said row address predecoder, a second current electrode coupled to said row selector, and a control electrode coupled to said output of said inverter.

Claim 17

The memory of claim 13, wherein said latch comprises: a first inverter having an input terminal for receiving said predecoded row address signal and an output terminal; a bipolar transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode coupled to said row selector for providing said predecoded row address signal, and a control electrode coupled to the output terminal of said first inverter; a first N-channel transistor having a first current electrode coupled to said output of said first inverter, a second current electrode coupled to said second current electrode of said bipolar transistor, and a control coupled to said input of said first inverter; a second N-channel transistor having a first current electrode coupled to said second current electrode of said bipolar transistor, a second current electrode coupled to a second power supply voltage terminal, and a control electrode coupled to said input of said first inverter; and a second inverter having an input terminal coupled to said second current electrode of said bipolar transistor and an output terminal coupled to said input terminal of said first inverter.

Claim 18

An asynchronous integrated circuit memory having a write cycle, indicated by a write enable single being in a first logic state, for writing data into the memory, and a read cycle, indicated by the write enable signal being in a second logic state, for reading data from the memory, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a word line and to a bit line pair, for receiving data from the bit line pair to which it is coupled, when the word line to which it is coupled is enabled; a row address buffer for receiving a row address signal and in response providing buffered complementary row address signals; a row predecoder for receiving said buffered complementary row address signals and for providing predecoded signals for selecting one of the word lines; a row selector coupled to said row predecoder, for receiving said predecoded row address signals, for performing a word line selection, and for changing such word line section in response to a change in said row address signal; bit line equalization means, coupled to the bit line pairs, for equalizing the voltages on the bit line pairs at the termination of the write cycle; a transfer gate coupled to said output of said row predecoder for receiving a first control signal and for preventing said row address predecoder from providing a new predecoder row address signal to said row selector when said first control signal is active; control means, for making said first control signal active in response to said write enable signal being in said first logic state, and for making said first control signal inactive in response to said write enable signal being in said second logic state, said first control signal being delayed for a predetermined time after said write enable signal transitions from said second logic state to said first logic state; and a latch for retaining said predecoded row address signal until a new predecoded row address signal is provided by said row predecoder.

Claim 19

An asynchronous integrated circuit memory having a write cycle, indicated by a write enable single being in a first logic state, for writing data into the memory, and a read cycle, indicated by the write enable signal being in a second logic state, for reading data from the memory, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a word line and to a bit line pair, for receiving data from the bit line pair to which it is coupled, when the word line to which it is coupled is enabled; a row address buffer for receiving a row address signal and in response providing buffered complementary row address signals; a row predecoder for receiving said buffered complementary row address signals and for providing predecoded signals for selecting one of the word lines; a row selector coupled to said row predecoder, for receiving said predecoded row address signals, for performing a word line selection, and for changing such word line section in response to a change in said row address signal; bit line equalization means, coupled to the bit line pairs, for equalizing the voltages on the bit line pairs at the termination of the write cycle; a transfer gate coupled to said output of said row predecoder for receiving a first control signal and for preventing said row address predecoder from providing a new predecoder row address signal to said row selector when said first control signal is active; control means, for making said first control signal active in response to said write enable signal being in said first logic state, and for making said first control signal inactive in response to said write enable signal being in said second logic state, said first control signal being delayed for a predetermined time after said write enable signal transitions from said second logic state to said first logic state; and a latch for retaining said predecoded row address signal until a new predecoded row address signal is provided by said row predecoder.

Claim 20

The memory of claim 16, wherein said row address predecoder comprises a NAND logic gate having a plurality of input terminals for receiving a plurality of said row address signals and an output terminal for providing the predecoded row address signal as a logical NAND of said plurality of row address signals.

Claim 21

The memory of claim 16, wherein said transfer gate comprises: a first transistor having a first current electrode coupled to said output of said row address predecoder, a second current electrode coupled to said row selector, and a control electrode for receiving said first control signal; an inverter having an input terminal for receiving said first control signal and an output terminal; and a second transistor having a first current electrode coupled to said output of said row address predecoder, a second current electrode coupled to said row selector, and a control electrode coupled to said output of said inverter.

Claim 22

The memory of claim 16, wherein said latch comprises: a first inverter having an input terminal for receiving said predecoded row address signal and an output terminal; a bipolar transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode coupled to said row selector for providing said predecoded row address signal, and a control electrode coupled to the output terminal of said first inverter; a first N-channel transistor having a first current electrode coupled to said output of said first inverter, a second current electrode coupled to said second current electrode of said bipolar transistor, and a control electrode coupled to said input of said first inverter; a second N-channel transistor having a first current electrode coupled to said second current electrode of said bipolar transistor, a second current electrode coupled to a second power supply voltage terminal, and a control electrode coupled to said input of said first inverter; and a second inverter having an input terminal coupled to said second current electrode of said bipolar transistor and an output terminal coupled to said input terminal of said first inverter.