Rectifier circuit including FETs of the same conductivity type

Claim 2

A rectifier circuit for deriving a direct voltage from a periodically varying input voltage to be applied to two input terminals, the circuit comprising: a first normally-off field-effect transistor (FET) having its main current path coupled between one of the input terminals and a first output terminal constituting one pole of the direct voltage, wherein the gate of the first FET is connected to a bias circuit for generating a substantially constant bias voltage between the gate and said one input terminal, the bias voltage being approximately equal to the threshold voltage of the first FET so as to reduce the effective threshold voltage of the first FET.

Claim 3

A rectifier circuit as claimed in claim 1, wherein the bias circuit comprises; a capacitance and a voltage-limiting element connected in parallel between the gate of the first FET and a first one of said input terminals, and a resistor and a first rectifier element connected in series between a second one of the two input terminals and the gate of the first FET.

Claim 4

A rectifier circuit as claimed in claim 1, wherein the bias circuit comprises; a first capacitance and a voltage-limiting element connected in parallel between the gate of the first FET and a first one of said input terminals, a first rectifier element and a second capacitance connected in series circuit to the input terminals, and a second rectifier element coupling a junction between the first rectifier element and the second capacitance to the gate of the first FET.

Claim 5

A rectifier circuit as claimed in claim 3, wherein said voltage-limiting element and said first and second rectifier elements each comprise a diode-connected FET of the same conductivity type as the first FET and wherein the voltage-limiting diode-connected FET has a threshold voltage at most equal to the threshold voltage of the first FET.

Claim 6

A rectifier circuit for a bridge rectifier arrangement for deriving a direct voltage from a substantially symmetrical alternating input voltage at first and second input terminals, comprising: a first normally off FET for each input terminal each with a separate bias circuit and a common first output terminal forming a first pole of the direct voltage, each bias circuit deriving a constant bias voltage of a value to compensate the threshold voltage of its respective first FET thereby to reduce the FET effective threshold voltage substantially to zero, each input terminal being further connected to a second output terminal via a respective second normally off FET of the same conductivity type, which second output terminal constitutes a second pole of the direct voltage, and the gate of each second FET being connected to the respective other input terminal.

Claim 7

A rectifier circuit for a bridge rectifier arrangement for deriving a direct voltage from a substantially symmetrical alternating input voltage at first and second input terminals, comprising: a first normally off FET for each input terminal each with a separate bias circuit and a common first output terminal forming a first pole of the direct voltage, each bias circuit deriving a constant bias voltage of a value to compensate the threshold voltage of its respective first FET thereby to reduce the FET effective threshold voltage substantially to zero, each input terminal being further connected to a second output terminal via a respective second normally off FET of the same conductivity type, which second output terminal constitutes a second pole of the direct voltage, and the gate of each second FET being connected to the respective other input terminal.

Claim 8

A bridge rectifier circuit as claimed in claim 5 wherein the bias circuits comprise a first bias circuit coupled to the first input terminal and a gate of one first FET and a second bias circuit coupled to the second input terminal and a gate of another first FET, the first bias circuit including a first capacitance coupled between the first input terminal and the gate of the one first FET and the second bias circuit including a second capacitance coupled between the second input terminal and the gate of the another first FET, means coupling a first series arrangement of a first rectifier element and a third capacitance between the gate of the one first FET and the second input terminal and a second series arrangement of a second rectifier element and a fourth capacitance between the gate of the another first FET and the first input terminal, and third and fourth rectifier elements connecting respective junctions in the first and second series arrangements to the second output terminal.

Claim 9

A bridge rectifier circuit as claimed in claim 6, further comprising first and second voltage limiting elements coupled in parallel with the first and second capacitances, respectively, and wherein the third and fourth capacitances are smaller than the first and second capacitances.

Claim 10

A bridge rectifier circuit for deriving a direct voltage from a substantially symmetrical alternating input voltage at two input terminals, comprising: a first normally off field effect transistor (FET) coupled to each input terminal with a separate bias circuit and a common first output terminal forming a first pole of the direct voltage, each, each input terminal being further connected to a second output terminal via a respective second normally off FET of the same conductivity type, which second output terminal constitutes a second pole of the direct voltage, the gate of each second FET being connected to a respective other input terminal, wherein, each bias circuit comprises a first capacitance connected between the gate of its respective first FET and the associated input terminal, and a first rectifying device which, at least for a fraction of the period of the input voltage, couples the gate of a respective first FET to a means for supplying an auxiliary voltage.

Claim 11

A bridge rectifier circuit for deriving a direct voltage from a substantially symmetrical alternating input voltage at two input terminals, comprising: a first normally off field effect transistor (FET) coupled to each input terminal with a separate bias circuit and a common first output terminal forming a first pole of the direct voltage, each, each input terminal being further connected to a second output terminal via a respective second normally off FET of the same conductivity type, which second output terminal constitutes a second pole of the direct voltage, the gate of each second FET being connected to a respective other input terminal, wherein, each bias circuit comprises a first capacitance connected between the gate of its respective first FET and the associated input terminal, and a first rectifying device which, at least for a fraction of the period of the input voltage, couples the gate of a respective first FET to a means for supplying an auxiliary voltage.

Claim 12

A bridge rectifier circuit as claimed in claim 8 for a bridge rectifier circuit whose input voltage is a substantially symmetrical alternating voltage, characterized in that the means for supplying an auxiliary voltage in each bias circuit comprise a second capacitance connected to the respective other input terminal, and a second rectifying device connected to the second output terminal.

Claim 13

A bridge rectifier circuit as claimed in claim 8 wherein, the input voltage is a substantially symmetrical alternating voltage, and the means for supplying an auxiliary voltage comprise the other input terminal.

Claim 14

A bridge rectifier circuit as claimed in claim 8, wherein the means for supplying an auxiliary voltage in each bias circuit comprise a second capacitance t, connected to the second output terminal, and a second rectifying device t, connected to the same input terminal as its associated first FET (T21,T22).

Claim 15

A bridge rectifier circuit as claimed in claim 8, further comprising a voltage-limiting element t coupled in parallel with a respective first capacitance t.

Claim 16

A bridge rectifier circuit as claimed in claim 8, wherein each first rectifying device includes a first additional normally-off FET of the same conductivity type as the first FET, and with the gate of each first additional normally-off FET connected to one terminal of its main current path.

Claim 17

A bridge rectifier circuit as claimed in claim 13, wherein the means for supplying an auxiliary voltage in each bias circuit comprise a respective second capacitance, connected to the respective other input terminal, and a respective second rectifying device, connected to the second output terminal.

Claim 18

A bridge rectifier circuit as claimed in claim 14, in which all of the FETs are integrated in a common semiconductor body, and each respective the second rectifying device comprises a junction between the first additional FET and the semiconductor body, which is connected to the one pole (V ss ) of the direct voltage.

Claim 19

A bridge rectifier circuit as claimed in claim 12, wherein the voltage-limiting element comprises a second normally-off FET of the same conductivity type as the first FET and with its gate connected to one terminal of its main current path, and wherein the second FET has a threshold voltage substantially equal to the threshold voltage of the first FET.

Claim 20

A rectifier circuit for deriving a direct voltage from a periodically varying input voltage to be applied to two input terminals, the circuit comprising: a first normally-off field-effect transistor (FET) having its main current path coupled between one of the input terminals and a first output terminal constituting one pole of the direct voltage, wherein the gate of the first FET is connected to a bias circuit for generating a substantially constant bias voltage between the gate and said one input terminal, the bias voltage reducing the effective threshold voltage of the first FET, and wherein the bias circuit comprises a first capacitance connected between the gate of the first FET and said one input terminal, and a first rectifying device which, at least for a fraction of the period of the input voltage, couples the gate of the first FET to means for supplying an auxiliary voltage.

Claim 21

A rectifier circuit for deriving a direct voltage from a periodically varying input voltage to be applied to two input terminals, the circuit comprising: a first normally-off field-effect transistor (FET) having its main current path coupled between one of the input terminals and a first output terminal constituting one pole of the direct voltage, wherein the gate of the first FET is connected to a bias circuit for generating a substantially constant bias voltage between the gate and said one input terminal, the bias voltage reducing the effective threshold voltage of the first FET, and wherein the bias circuit comprises a first capacitance connected between the gate of the first FET and said one input terminal, and a first rectifying device which, at least for a fraction of the period of the input voltage, couples the gate of the first FET to means for supplying an auxiliary voltage.

Claim 22

A rectifier circuit as claimed in claim 17, wherein the first rectifying device includes a first additional normally-off FET of the same conductivity type as the first FET and with the gate of the first additional normally-off FET connected to one terminal of its main current path.

Claim 23

A rectifier circuit as claimed in claim 17, further comprising a voltage-limiting element coupled in parallel with the first capacitance.

Claim 24

A rectifier circuit as claimed in claim 19, wherein the voltage-limiting element comprises a second normally-off FET of the same conductivity type as the first FET and with its gate connected to one terminal of its main current path, and wherein the second FET has a threshold voltage substantially equal to the threshold voltage of the first FET.

Claim 25

A rectifier circuit as claimed in claim 20, wherein the means for supplying an auxiliary voltage in the bias circuit comprise a second capacitance connected to a second output terminal, and a second rectifying device connected to said one input terminal.

Claim 26

A rectifier circuit as claimed in claim 20, wherein the input voltage is a substantially symmetrical alternating voltage, and the means for supplying an auxiliary voltage comprise the other input terminal.

Claim 27

A rectifier circuit as claimed in claim 17, wherein the means for supplying an auxiliary voltage in the bias circuit comprise a second capacitance connected to a second output terminal, and a second rectifying device connected to said one input terminal.

Claim 28

A rectifier circuit as claimed in claim 23, wherein the second rectifying device comprises a second normally-off FET of the same conductivity type as the first FET and with its gate connected to one terminal of its main current path.