US5268332A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of integrated circuit fabrication having planarized dielectrics
Assignee: Agere Systems LLC
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Filing: 1992-11-12
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Granted: 1993-12-07
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Expires: 2012-11-12
Abstract
Abstract A method for forming an integrated circuit with a planarized dielectric is disclosed. Runners and gates are covered with a protective dielectric layer. Then a conventional dielectric is deposited and planarized over the entire circuit surface. When windows are opened to runners and to source/drain regions, the protective dielectric helps to slow the etch process over the runner, thus protecting the runner from damage during the extra time required for the etch process to reach the source or drain.
Inventors
- 👤 Dayo Alugbin
- 👤 Franklin D. Nkansah
- 👤 Kolawole R. Olasupo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:00
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10W20/092
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
111 words
A method of integrated circuit manufacture comprising: forming a raised topographic feature upon a substrate; forming a first layer upon said topographic feature; said first layer not covering said substrate and having a predetermined thickness; forming a second layer upon said first layer and upon said substrate; planarizing said second layer; selectively etching said second layer and said first layer to create first and second openings, said first opening being over said topographic feature, and said second opening being over said substrate; the thickness of said first layer being chosen so that said first opening exposes said topographic feature at approximately the same time that said second opening exposes said substrate.
Claim 2
Independent Claim
111 words
A method of integrated circuit manufacture comprising: forming a raised topographic feature upon a substrate; forming a first layer upon said topographic feature; said first layer not covering said substrate and having a predetermined thickness; forming a second layer upon said first layer and upon said substrate; planarizing said second layer; selectively etching said second layer and said first layer to create first and second openings, said first opening being over said topographic feature, and said second opening being over said substrate; the thickness of said first layer being chosen so that said first opening exposes said topographic feature at approximately the same time that said second opening exposes said substrate.
Claim 3
Dependent Claim
14 words
The method of claim 1 in which said first layer is formed from TEOS.
Claim 4
Dependent Claim
14 words
The method of claim 1 in which said second layer is formed from BPTEOS.
Claim 5
Dependent Claim
25 words
The method of claim 1 in which said second layer is a bilayer comprising a layer formed from TEOS under a layer formed from BPTEOS.
Claim 6
Dependent Claim
61 words
The method of claim 1 in which the thickness of said first layer is chosen in accord with the formula: ##EQU2## where t 4 =thickness of first layer, t 2 =thickness of second layer over substrate, t 1 =thickness of second layer over topographic feature, r 1 =etch rate of said second layer, r 3 =etch rate of said first layer.
Claim 7
Dependent Claim
15 words
The method of claim 1 in which said first and second openings have tapered sides.
Claim 8
Dependent Claim
16 words
The method of claim 1 in which said first and second openings are filled with aluminum.
Claim 9
Dependent Claim
13 words
The method of claim 1 in which said topographic feature is a runner.
Claim 10
Independent Claim
102 words
A method of semiconductor integrated circuit fabrication comprising: forming a field oxide upon a semiconductor substrate; forming source, gate, and drain upon said substrate; forming a runner upon said field oxide, said runner having a first layer of TEOS upon it; forming a second layer of TEOS over said first layer of TEOS, and contacting said source, gate, and drain; forming a layer of BPTEOS over said second layer of TEOS; smoothing or planarizing said layer of BPTEOS; selectively etching said BPTEOS layer and said first and second TEOS layers to expose said runner and said substrate at approximately the same time.
Claim 11
Independent Claim
102 words
A method of semiconductor integrated circuit fabrication comprising: forming a field oxide upon a semiconductor substrate; forming source, gate, and drain upon said substrate; forming a runner upon said field oxide, said runner having a first layer of TEOS upon it; forming a second layer of TEOS over said first layer of TEOS, and contacting said source, gate, and drain; forming a layer of BPTEOS over said second layer of TEOS; smoothing or planarizing said layer of BPTEOS; selectively etching said BPTEOS layer and said first and second TEOS layers to expose said runner and said substrate at approximately the same time.
References Cited (Backward Citations)
US4814041A
Cited
US5022958A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |