Method of making DRAM having a stacked capacitor

Claim 1

A method of manufacturing a DRAM having a stacked capacitor, said method comprising: providing a silicon substrate with a field oxide layer 2, a gate oxide layer 3, gate electrode and gate electrode lines 4A, 4B, oxide spacers 5 and drain and source electrodes on the silicon substrate 1 forming a MOSFET 25; depositing a first insulating layer 7 on the entire surface of the resulting structure comprising the gate electrode and gate electrode lines 4A, 4B; forming a first contact hole 7A by removing a portion of the first insulating layer 7 on the source electrode 6B to expose a portion of the source electrode 6B; depositing a first conducting layer 8 for charge storage electrode on the first insulating layer 7 and on the exposed source electrode 6B through the first contact hole 7A electrically connecting the source electrode 6B; depositing a second insulating layer 9 on the entire surface of the resulting structure; depositing a first photoresistive layer 10 on the second insulating layer 9; forming a first pattern mask 10A having a linear dimension in the word line direction which is greater than the linear dimension in the bit line direction by removing the first photoresistive layer 10 from the second insulating layer 9 to expose the second insulating layer 9 except for a remaining portion of the first photoresistive layer 10A and the underlying second insulating layer 9 positioned over the source electrode 6B; removing the exposed second insulating layer 9 utilizing the first pattern mask 10A thereby exposing the first conducting layer 8 except for remaining portions of the first conducting layer positioned over the source electrode 6B, of the second insulating layer 9A and of the first photoresistive layer 10A overlying the first conducting layer 8; removing the remaining portion of the first photoresistive layer 10A overlying the remaining second insulating layer 9A; depositing a second conductive layer 11 for charge storage electrode over the resulting structure comprising the remaining portion of the second insulating layer 9A overlying the first conducting layer 8; depositing a second photoresistive layer 12 on the second conducting layer 11; forming a mask pattern 12A for charge storage electrode by forming a second pattern mask 12A having a linear dimension greater than the linear dimension of the first pattern mask 10A in the bit line direction and with the second pattern mask 12A having a linear dimension smaller than the linear dimension of the first pattern mask 10A in the word line direction over a predetermined region positioned above the source region 6B by removing the second photoresistive layer 12 to expose the second conducting layer 11 except for the remaining portion of the second conducting layer 11B underlying the second pattern mask 12A; etching the exposed portion of the second conducting layer 11 utilizing the second pattern mask 12A by an anisotropic etching process; removing the remaining portion of the second insulating layer 9A enclosed between the remaining portion of the second conducting layer 11B for charge storage electrode and the first conducting layer 8 for charge storage electrode by a wet etching process thereby forming a tunnel space 9B between the second conducting layer 11B and the first conducting layer 8 in the word line direction; removing the exposed first conducting layer 8 for charge storage electrode 8 by anisotropically etching utilizing the second pattern mask 12A to thereby form a charge storage electrode 11A consisting of the remaining second conducting layer 11B and the first conducting layer 8 and a tunnel space 9B overlying the source electrode 6B and then removing the second pattern mask 12A; forming a capacitive dielectric layer 13 on the entire surface of the charge storage electrode 11A and on the walls 9C of the tunnel space 9B; depositing a third conducting layer 14 for plate electrode, on the entire surface of the charge storage electrode 11A including on the capacitive dielectric layer formed on the walls of the tunnel space 9B; and forming a plate electrode 14A by removing a predetermined portion of the third conducting layer 14 from a portion overlying 14C the drain electrode 6A by a mask patterning process to thereby form a stack capacitor 18 having an increased area for the charge storage electrode 11A thereby increasing the capacitance of the stack capacitor.

Claim 2

A method of manufacturing a DRAM having a stacked capacitor, said method comprising: providing a silicon substrate with a field oxide layer 2, a gate oxide layer 3, gate electrode and gate electrode lines 4A, 4B, oxide spacers 5 and drain and source electrodes on the silicon substrate 1 forming a MOSFET 25; depositing a first insulating layer 7 on the entire surface of the resulting structure comprising the gate electrode and gate electrode lines 4A, 4B; forming a first contact hole 7A by removing a portion of the first insulating layer 7 on the source electrode 6B to expose a portion of the source electrode 6B; depositing a first conducting layer 8 for charge storage electrode on the first insulating layer 7 and on the exposed source electrode 6B through the first contact hole 7A electrically connecting the source electrode 6B; depositing a second insulating layer 9 on the entire surface of the resulting structure; depositing a first photoresistive layer 10 on the second insulating layer 9; forming a first pattern mask 10A having a linear dimension in the word line direction which is greater than the linear dimension in the bit line direction by removing the first photoresistive layer 10 from the second insulating layer 9 to expose the second insulating layer 9 except for a remaining portion of the first photoresistive layer 10A and the underlying second insulating layer 9 positioned over the source electrode 6B; removing the exposed second insulating layer 9 utilizing the first pattern mask 10A thereby exposing the first conducting layer 8 except for remaining portions of the first conducting layer positioned over the source electrode 6B, of the second insulating layer 9A and of the first photoresistive layer 10A overlying the first conducting layer 8; removing the remaining portion of the first photoresistive layer 10A overlying the remaining second insulating layer 9A; depositing a second conductive layer 11 for charge storage electrode over the resulting structure comprising the remaining portion of the second insulating layer 9A overlying the first conducting layer 8; depositing a second photoresistive layer 12 on the second conducting layer 11; forming a mask pattern 12A for charge storage electrode by forming a second pattern mask 12A having a linear dimension greater than the linear dimension of the first pattern mask 10A in the bit line direction and with the second pattern mask 12A having a linear dimension smaller than the linear dimension of the first pattern mask 10A in the word line direction over a predetermined region positioned above the source region 6B by removing the second photoresistive layer 12 to expose the second conducting layer 11 except for the remaining portion of the second conducting layer 11B underlying the second pattern mask 12A; etching the exposed portion of the second conducting layer 11 utilizing the second pattern mask 12A by an anisotropic etching process; removing the remaining portion of the second insulating layer 9A enclosed between the remaining portion of the second conducting layer 11B for charge storage electrode and the first conducting layer 8 for charge storage electrode by a wet etching process thereby forming a tunnel space 9B between the second conducting layer 11B and the first conducting layer 8 in the word line direction; removing the exposed first conducting layer 8 for charge storage electrode 8 by anisotropically etching utilizing the second pattern mask 12A to thereby form a charge storage electrode 11A consisting of the remaining second conducting layer 11B and the first conducting layer 8 and a tunnel space 9B overlying the source electrode 6B and then removing the second pattern mask 12A; forming a capacitive dielectric layer 13 on the entire surface of the charge storage electrode 11A and on the walls 9C of the tunnel space 9B; depositing a third conducting layer 14 for plate electrode, on the entire surface of the charge storage electrode 11A including on the capacitive dielectric layer formed on the walls of the tunnel space 9B; and forming a plate electrode 14A by removing a predetermined portion of the third conducting layer 14 from a portion overlying 14C the drain electrode 6A by a mask patterning process to thereby form a stack capacitor 18 having an increased area for the charge storage electrode 11A thereby increasing the capacitance of the stack capacitor.

Claim 9

A method of manufacturing a DRAM having a stacked capacitor, said method comprising: providing a silicon substrate with a field oxide layer 2, a gate oxide layer 3, gate electrode and gate electrode lines 4A, 4B, oxide spacers 5 and drain and source electrodes on the silicon substrate 1 forming a MOSFET 25; depositing a first insulating layer 7 on the entire surface of the resulting structure comprising the gate electrode and gate electrode lines 4A, 4B; forming a first contact hole 7A by removing a portion of the first insulating layer on the source electrode 6B to expose a portion of the source electrode 6B; depositing a first conducting layer 8 for charge storage electrode of polysilicon on the first insulating layer 7 and on the exposed source electrode 6B through the first contact hole 7A electrically connecting the source electrode 6B; depositing a second insulating layer 9 on the entire surface of the resulting structure; depositing a first photoresistive layer 10 on the second insulating layer 9; forming a first pattern mask 10A having a linear dimension in the word line direction which is greater than the linear dimension in the bit line direction by removing the first photoresistive layer 10 from the second insulating layer 9 to expose the second insulating layer 9 except for a remaining portion of the first photoresistive layer 10A and the underlying second insulating layer 9 positioned over the source electrode 6B; removing the exposed second insulating layer 9 by anisotropic etching the layer 9 utilizing the first pattern mask 10A thereby exposing the first conducting layer 8 except for remaining portions of the first conducting layer positioned over the source electrode 6B, of the second insulating layer 9A and of the first photoresistive layer 10A overlying the first conducting layer 8; removing the remaining portion of the first photoresistive layer 10A overlying the remaining second insulating layer 9A; depositing a second conductive layer 11 for charge storage electrode of polysilicon as thick as 1000 Angstroms over the resulting structure comprising the remaining portion of the second insulating layer 9A overlying the first conducting layer 8; depositing a second photoresistive layer 12 on the second conducting layer 11; forming a mask pattern 12A for charge storage electrode by forming a second pattern mask 12A having a linear dimension greater than the linear dimension of the first pattern mask 10A in the bit line direction and with the second pattern mask 12A having a linear dimension smaller than the linear dimension of the first pattern mask 10A in the word line direction over a predetermined region positioned above the source region 6B by removing the second photoresistive layer 12 to expose the second conducting layer 11 except for the remaining portion of the second conducting layer 11B underlying the second pattern mask 12A; etching the exposed portion of the second conducting layer 11 utilizing the second pattern mask 12A by an anisotropic etching process; removing the remaining portion of the second insulating layer 9A enclosed between the second conducting layer 11B for charge storage electrode and the first conducting layer 8 for charge storage electrode by a wet etching process thereby forming a tunnel space 9B between the second conducting layer 11B and the first conducting layer 8 in the word line direction; removing the exposed first conducting layer 8 for charge storage electrode 8 by anisotropically etching utilizing the second pattern mask 12A to thereby form a charge storage electrode 11A consisting of the remaining second conducting layer 11B and the first conducting layer 8 and a tunnel space 9B overlying the source electrode 6B and then removing the second pattern mask 12A; forming a capacitive dielectric layer 13 on the entire surface of the charge storage electrode 11A and on the walls 9C of the tunnel space 9B; depositing a third conducting layer 14 for plate electrode, of polysilicon as thick as 1500 Angstroms on the entire surface of the charge storage electrode 11 A including on the capacitive dielectric layer formed on the walls of the tunnel space 9B; forming a plate electrode 14A by removing a predetermined portion of the third conducting layer 14 by a mask patterning process to thereby form a stack capacitor 18; depositing a third insulating layer 15 on the entire surface of the resulting structure comprising the plate electrode 14A; removing the third insulating layer 15 deposited on the drain electrode 6A thereby forming a second contact hole 16 and exposing the surface of the drain electrode 6A; and forming a bit line electrode 17 on the third insulating layer 15 and on the first insulating layer 7 exposed on the wall of the second contact hole 16 to connect the bit line electrode through the second contact hole 16 to the drain of the MOSFET thereby increasing the area for the charge storage electrode 11A such that the capacitance of the stack capacitor is increased.

Claim 10

A method of manufacturing a DRAM having a stacked capacitor, said method comprising: providing a silicon substrate with a field oxide layer 2, a gate oxide layer 3, gate electrode and gate electrode lines 4A, 4B, oxide spacers 5 and drain and source electrodes on the silicon substrate 1 forming a MOSFET 25; depositing a first insulating layer 7 on the entire surface of the resulting structure comprising the gate electrode and gate electrode lines 4A, 4B; forming a first contact hole 7A by removing a portion of the first insulating layer on the source electrode 6B to expose a portion of the source electrode 6B; depositing a first conducting layer 8 for charge storage electrode of polysilicon on the first insulating layer 7 and on the exposed source electrode 6B through the first contact hole 7A electrically connecting the source electrode 6B; depositing a second insulating layer 9 on the entire surface of the resulting structure; depositing a first photoresistive layer 10 on the second insulating layer 9; forming a first pattern mask 10A having a linear dimension in the word line direction which is greater than the linear dimension in the bit line direction by removing the first photoresistive layer 10 from the second insulating layer 9 to expose the second insulating layer 9 except for a remaining portion of the first photoresistive layer 10A and the underlying second insulating layer 9 positioned over the source electrode 6B; removing the exposed second insulating layer 9 by anisotropic etching the layer 9 utilizing the first pattern mask 10A thereby exposing the first conducting layer 8 except for remaining portions of the first conducting layer positioned over the source electrode 6B, of the second insulating layer 9A and of the first photoresistive layer 10A overlying the first conducting layer 8; removing the remaining portion of the first photoresistive layer 10A overlying the remaining second insulating layer 9A; depositing a second conductive layer 11 for charge storage electrode of polysilicon as thick as 1000 Angstroms over the resulting structure comprising the remaining portion of the second insulating layer 9A overlying the first conducting layer 8; depositing a second photoresistive layer 12 on the second conducting layer 11; forming a mask pattern 12A for charge storage electrode by forming a second pattern mask 12A having a linear dimension greater than the linear dimension of the first pattern mask 10A in the bit line direction and with the second pattern mask 12A having a linear dimension smaller than the linear dimension of the first pattern mask 10A in the word line direction over a predetermined region positioned above the source region 6B by removing the second photoresistive layer 12 to expose the second conducting layer 11 except for the remaining portion of the second conducting layer 11B underlying the second pattern mask 12A; etching the exposed portion of the second conducting layer 11 utilizing the second pattern mask 12A by an anisotropic etching process; removing the remaining portion of the second insulating layer 9A enclosed between the second conducting layer 11B for charge storage electrode and the first conducting layer 8 for charge storage electrode by a wet etching process thereby forming a tunnel space 9B between the second conducting layer 11B and the first conducting layer 8 in the word line direction; removing the exposed first conducting layer 8 for charge storage electrode 8 by anisotropically etching utilizing the second pattern mask 12A to thereby form a charge storage electrode 11A consisting of the remaining second conducting layer 11B and the first conducting layer 8 and a tunnel space 9B overlying the source electrode 6B and then removing the second pattern mask 12A; forming a capacitive dielectric layer 13 on the entire surface of the charge storage electrode 11A and on the walls 9C of the tunnel space 9B; depositing a third conducting layer 14 for plate electrode, of polysilicon as thick as 1500 Angstroms on the entire surface of the charge storage electrode 11 A including on the capacitive dielectric layer formed on the walls of the tunnel space 9B; forming a plate electrode 14A by removing a predetermined portion of the third conducting layer 14 by a mask patterning process to thereby form a stack capacitor 18; depositing a third insulating layer 15 on the entire surface of the resulting structure comprising the plate electrode 14A; removing the third insulating layer 15 deposited on the drain electrode 6A thereby forming a second contact hole 16 and exposing the surface of the drain electrode 6A; and forming a bit line electrode 17 on the third insulating layer 15 and on the first insulating layer 7 exposed on the wall of the second contact hole 16 to connect the bit line electrode through the second contact hole 16 to the drain of the MOSFET thereby increasing the area for the charge storage electrode 11A such that the capacitance of the stack capacitor is increased.