US5267250A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for detection of an erroneous selection signal supplied to selection means
Assignee: NEC Corp
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Filing: 1990-12-17
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Granted: 1993-11-30
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Expires: 2010-12-17
Abstract
Abstract An erroneous selection signal detecting circuit in a data transfer system. Conventional error detecting systems may not be capable of detecting errors in the selection signal generating circuit using available parity of checksum procedures. The selector means in the present invention selects one of a plurality of input signals on the basis of selection information. This information is applied both to appropriate selection circuits and to two additional selecting circuits also continually receiving fixed data input values. The outputs from these additional circuits are compared to the selection signals through EXCLUSIVE-OR gates, a particular logical indication from the EXCLUSIVE-OR gates indicating a malfunction.
Inventors
- 👤 Izushi Uehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:06
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
146 words
A circuit arrangement for detection of an erroneous selection signal comprising: selection information generating means for generating selection information; transfer means receiving said selection information transferred by said transfer means for selecting one of a plurality of input signals on a basis of said selection information; fault detection information generating means receiving said selection information through said transfer means for generating fault detection information having a predetermined relationship with said selection information; and fault detection means, receiving said selection information directly from said selection information generating means without passing though said transfer means and receiving said fault detection information from si fault detection generating means, for examining whether or not said selection information has said predetermined relationship with said fault detection information and for outputting an error signal when said selection information as directly received does not have said predetermined relationship with said fault detection information.
Claim 2
Dependent Claim
146 words
A circuit arrangement for detection of an erroneous selection signal comprising: selection information generating means for generating selection information; transfer means receiving said selection information transferred by said transfer means for selecting one of a plurality of input signals on a basis of said selection information; fault detection information generating means receiving said selection information through said transfer means for generating fault detection information having a predetermined relationship with said selection information; and fault detection means, receiving said selection information directly from said selection information generating means without passing though said transfer means and receiving said fault detection information from si fault detection generating means, for examining whether or not said selection information has said predetermined relationship with said fault detection information and for outputting an error signal when said selection information as directly received does not have said predetermined relationship with said fault detection information.
Claim 3
Dependent Claim
112 words
A circuit for detecting an erroneous selection signal in a data transfer system, comprising: a plurality of data selection circuits, each receiving data to be transferred; a decoder for selecting the data to be transferred from each selection circuit and accordingly providing selection signals to each of said data selection circuits; a pair of error detecting circuits, each receiving the selection signals applied to the plurality of data selection circuits and also continually receiving fixed input signals; means for comparing the outputs from the pair of error detecting circuits to input signals to the decoder, to detect from the output of the comparing means if the selection signal is correct or erroneous.
Claim 4
Dependent Claim
112 words
A circuit for detecting an erroneous selection signal in a data transfer system, comprising: a plurality of data selection circuits, each receiving data to be transferred; a decoder for selecting the data to be transferred from each selection circuit and accordingly providing selection signals to each of said data selection circuits; a pair of error detecting circuits, each receiving the selection signals applied to the plurality of data selection circuits and also continually receiving fixed input signals; means for comparing the outputs from the pair of error detecting circuits to input signals to the decoder, to detect from the output of the comparing means if the selection signal is correct or erroneous.
Claim 5
Dependent Claim
30 words
The circuit of claim 2, in which the input to the decoder is a flip-flop, the decoder providing data selection signals in response to the output signals from the flip-flop.
Claim 6
Dependent Claim
34 words
The circuit of claim 2, in which each of said plurality of selection circuits include a plurality of AND gates, each of said AND gates having one data input and one data selection input.
Claim 7
Dependent Claim
24 words
The circuit of claim 4, in which the output of each of said selection circuit AND gates provide an input to an OR gate.
Claim 8
Dependent Claim
38 words
The circuit of claim 2, wherein each of said error detecting circuits include a plurality of AND gates, each AND gate receiving at one input a data selection signal and at the other input a predetermined fixed signal.
Claim 9
Dependent Claim
27 words
The circuit of claim 6, in which the outputs of the plurality of AND gates form the inputs to an OR gate in each error detecting circuit.
Claim 10
Dependent Claim
72 words
The circuit of claim 7, in which the output signal of each OR gate forms the input to one of the other of a pair of EXCLUSIVE OR gates, the other input to each EXCLUSIVE OR gates being the data selection signal, the outputs of each EXCLUSIVE OR gate forming the inputs to an OR gate, whereby the output of the AND gate indicates if an erroneous selection signal has been generated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-29 | 1997-05-31 | 1997-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-29 | 2001-05-31 | 2001-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-29 | 2005-05-31 | 2005-11-30 | $7700.00 | Window Closed / Lapsed |