Electrically programmable read only memory device with reliable sense amplifier circuit

Claim 2

A non-volatile semiconductor memory device fabricated on a single semiconductor chip, comprising: a) a memory cell array having a plurality of non-volatile memory elements arranged in rows and columns, said columns of said non-volatile memory elements being divided into two sections so as to form first and second memory sections, said non-volatile memory elements of said first memory section being respectively paired with said non-volatile memory elements of said second memory section so as to form a plurality of memory cells for storing data bits, respectively; b) a plurality of word lines respectively coupled with said rows of said non-volatile memory elements, and selectively activating said memory cells; c) first digit lines respectively coupled with the columns of said non-volatile memory elements of said first memory section; d) second digit lines respectively coupled with the columns of said non-volatile memory elements of said second memory section, and respectively paired with said first digit lines so as to form digit line pairs for propagating data bits read out from activating memory cells, each of said data bits read out from said activated memory cells being in the form of a difference in voltage level; e) a column selecting unit having first and second output nodes, and coupled with said digit line pairs for interconnecting one of said digit line pairs and said first and second output nodes thereof; and f) a sensing amplifier unit comprising f-1) a first current mirror circuit coupled between a source of power voltage level and a first input node of said first current mirror circuit for allowing a first current to pass therebetween, and operative to control the amount of said first current, f-2) a first gate means responsive to the voltage level at said first output node, and relaying the voltage level at said first output node to said first input node, f-3) a second current mirror circuit coupled between said source of power voltage level and a second input node of said second current mirror circuit for allowing a second current to pass therethrough, and operative to control the amount of said second current, f-4) a second gate means responsive to the voltage level at said second output node, and relaying the voltage level at said second output node to said second input node, f-5) a third current mirror circuit having a first current path assigned to said first current, a second current path assigned to said second current, a third input node supplied with said first current for concurrently controlling the conductances of said first and second current paths, and a fourth input node supplied with said second current path, f-6) an output inverting circuit having an input node coupled with said fourth input node and producing an output data signal, and f-7) a ratio controlling circuit responsive to said output data signal and operative to change a ratio of the conductance of said second current path to said conductance of said first current path.

Claim 3

A non-volatile semiconductor memory device fabricated on a single semiconductor chip as set forth in claim 1, in which said each of said first and second gate means comprises an inverting circuit having an input node coupled to one of said first and second output nodes, and a gate transistor coupled between one of said first and second output nodes and one of said first and second input nodes and gated by said inverting circuit.

Claim 4

A non-volatile semiconductor memory device fabricated on a single semiconductor chip as set forth in claim 2, in which each of said first and second current mirror circuits comprises a first transistor with a first channel conductivity type coupled between a first source of voltage level and one of said first and second input nodes, and a second transistor with said second channel conductivity type coupled between said first source of voltage level and one of said third and fourth input nodes, said first and second transistors being gated by said one of said first and second input nodes.

Claim 5

A non-volatile semiconductor memory device fabricated on a single semiconductor chip as set forth in claim 3, in which said first current path is established in a third transistor of a second channel conductivity type opposite to said first channel conductivity type, said third transistor being gated by said third input node.

Claim 6

A non-volatile semiconductor memory device fabricated on a single semiconductor chip, comprising: a) a memory cell array having a plurality of non-volatile memory elements arranged in rows and columns, said columns of said non-volatile memory elements being divided into two sections so as to form first and second memory sections, said non-volatile memory elements of said first memory section being respectively paired with said non-volatile memory elements of said second memory section so as to form a plurality of memory cells for storing data bits, respectively; b) a plurality of word lines respectively coupled with said rows of said non-volatile memory elements, and selectively activating said memory cells; c) first digit lines respectively coupled with the columns of said non-volatile memory elements of said first memory section; d) second digit lines respectively coupled with the columns of said non-volatile memory elements of said second memory section, and respectively paired with said first digit lines so as to form digit line pairs for propagating data bits read out from activated memory cells, each of said data bits read out from said activated memory cells being in the form of a difference in voltage levels; e) a column selecting unit having first and second output nodes, and coupled with said digit line pairs for interconnecting one of said digit line pairs and said first and second output nodes thereof; and f) a sense amplifier unit comprising f-1) a first current mirror circuit coupled between a source of power voltage level and a first input node of said first current mirror circuit for allowing a first current to pass therebetween, and operative to control the amount of said first current, f-2) a first gate means responsive to the voltage level at said first output node, and relaying the voltage level at said first output node to said first input node, f-3) a second current mirror circuit coupled between said source of power voltage level and a second input node of said second current mirror circuit for allowing a second current to pass therethrough, and operative to control the amount of said second current, each of said first and second current mirror circuits comprising a first transistor with a first channel conductivity type coupled between a first source of voltage level and one of said first and second input nodes, and a second transistor with said second channel conductivity type coupled between said first source of voltage level and one of said third and fourth input nodes, said first and second transistors being gated from said one of said first and second input nodes f-4) a second gate means responsive to the voltage level at said second output node, and relaying the voltage level at said second output node to said second input node, each of said first and second gate means comprising an inverting circuit having an input node coupled to one of said first and second output nodes, and a gate transistor coupled between one of said first and second output nodes and one of said first and second input nodes and gated from said inverting circuit, f-5) a third current mirror circuit having a first current path assigned to said first current, a second current path assigned to said second current, a third input node supplied with said first current for concurrently controlling the conductances of said first and second current paths, and a fourth input node supplied with said second current path, said first current path being established in a third transistor of a second channel conductivity type opposite to said first channel conductivity type, said third transistor being gated from said third input node, said second current path being formed by at least fourth and fifth transistors with said second channel conductivity type and coupled in parallel between said fourth input node and said ratio controlling circuit, said at least fourth and fifth transistors being gated from said third input node, f-6) an output inverting circuit having an input node coupled with said fourth input node and producing an output data signal, and f-7) a ratio controlling circuit responsive to said output data signal and operative to change a ratio of the conductance of said second current path to said conductance of said first current path.

Claim 7

A non-volatile semiconductor memory device fabricated on a single semiconductor chip, comprising: a) a memory cell array having a plurality of non-volatile memory elements arranged in rows and columns, said columns of said non-volatile memory elements being divided into two sections so as to form first and second memory sections, said non-volatile memory elements of said first memory section being respectively paired with said non-volatile memory elements of said second memory section so as to form a plurality of memory cells for storing data bits, respectively; b) a plurality of word lines respectively coupled with said rows of said non-volatile memory elements, and selectively activating said memory cells; c) first digit lines respectively coupled with the columns of said non-volatile memory elements of said first memory section; d) second digit lines respectively coupled with the columns of said non-volatile memory elements of said second memory section, and respectively paired with said first digit lines so as to form digit line pairs for propagating data bits read out from activated memory cells, each of said data bits read out from said activated memory cells being in the form of a difference in voltage levels; e) a column selecting unit having first and second output nodes, and coupled with said digit line pairs for interconnecting one of said digit line pairs and said first and second output nodes thereof; and f) a sense amplifier unit comprising f-1) a first current mirror circuit coupled between a source of power voltage level and a first input node of said first current mirror circuit for allowing a first current to pass therebetween, and operative to control the amount of said first current, f-2) a first gate means responsive to the voltage level at said first output node, and relaying the voltage level at said first output node to said first input node, f-3) a second current mirror circuit coupled between said source of power voltage level and a second input node of said second current mirror circuit for allowing a second current to pass therethrough, and operative to control the amount of said second current, each of said first and second current mirror circuits comprising a first transistor with a first channel conductivity type coupled between a first source of voltage level and one of said first and second input nodes, and a second transistor with said second channel conductivity type coupled between said first source of voltage level and one of said third and fourth input nodes, said first and second transistors being gated from said one of said first and second input nodes f-4) a second gate means responsive to the voltage level at said second output node, and relaying the voltage level at said second output node to said second input node, each of said first and second gate means comprising an inverting circuit having an input node coupled to one of said first and second output nodes, and a gate transistor coupled between one of said first and second output nodes and one of said first and second input nodes and gated from said inverting circuit, f-5) a third current mirror circuit having a first current path assigned to said first current, a second current path assigned to said second current, a third input node supplied with said first current for concurrently controlling the conductances of said first and second current paths, and a fourth input node supplied with said second current path, said first current path being established in a third transistor of a second channel conductivity type opposite to said first channel conductivity type, said third transistor being gated from said third input node, said second current path being formed by at least fourth and fifth transistors with said second channel conductivity type and coupled in parallel between said fourth input node and said ratio controlling circuit, said at least fourth and fifth transistors being gated from said third input node, f-6) an output inverting circuit having an input node coupled with said fourth input node and producing an output data signal, and f-7) a ratio controlling circuit responsive to said output data signal and operative to change a ratio of the conductance of said second current path to said conductance of said first current path.

Claim 8

A non-volatile semiconductor memory device fabricated on a single semiconductor chip, comprising: a) a memory cell array having a plurality of non-volatile memory elements arranged in rows and columns, said columns of said non-volatile memory elements being divided into two sections so as to form first and second memory sections, said non-volatile memory elements of said first memory section being respectively paired with said non-volatile memory elements of said second memory section so as to form a plurality of memory cells for storing data bits, respectively; b) a plurality of word lines respectively coupled with said rows of said non-volatile memory elements, and selectively activating said memory cells; c) first digit lines respectively coupled with the columns of said non-volatile memory elements of said first memory section; d) second digit lines respectively coupled with the columns of said non-volatile memory elements of said second memory section, and respectively paired with said first digit lines so as to form digit line pairs for propagating data bits read out from activated memory cells, each of said data bits read out from said activated memory cells being in the form of a difference in voltage levels; e) a column selecting unit having first and second output nodes, and coupled wit said digit line pairs for interconnecting one of said digit line pairs and said first and second output nodes thereof; and f) a sensing amplifier unit comprising f-1) a first current mirror circuit coupled between a source of power voltage level and a first input node of said first current mirror circuit for allowing a first current to pass therebetween, and operative to control the amount of said first current, f-2) a first gate means responsive to the voltage level at said first output node, and relaying the voltage level at said first output node to said first input node, f-3) a second current mirror circuit coupled between said source of power voltage level and a second input node of said second current mirror circuit for allowing a second current to pass therethrough, and operative to control the amount of said second current, each of said first and second current mirror circuits comprising a first transistor with a first channel conductivity type coupled between a first source of voltage level and one of said first and second input nodes, and a second transistor with said second channel conductivity type coupled between said first source of voltage level and one of said third and fourth input nodes, said first and second transistors being gated from said one of said first and second input nodes f-4) a second gate means responsive to the voltage level at said second output node, and relaying the voltage level at said second output node to said second input node, each of said first and second gate means comprising an inverting circuit having an input node coupled to one of said first and second output nodes, and a gate transistor coupled between one of said first and second output nodes and one of said first and second input nodes and gated from said inverting circuit f-5) a third current mirror circuit having a first current path assigned to said first current, a second current path assigned to said second current, a third input node supplied with said first current for concurrently controlling the conductances of said first and second current paths, and a fourth input node supplied with said second current path, said first current path being formed by at least ninth and tenth transistors with a second channel conductivity type opposite to said first channel conductivity type coupled in parallel between said third input node and said ratio controlling circuit, said ninth and tenth transistors being gated from said third input node, f-6) an output inverting circuit having an input node coupled with said fourth input node and producing an output data signal, and f-7) a ratio controlling circuit responsive to said output data signal and operative to change a ratio of the conductance of said second current path to said conductance of said first current path.

Claim 9

A non-volatile semiconductor memory device fabricated on a single semiconductor chip, comprising: a) a memory cell array having a plurality of non-volatile memory elements arranged in rows and columns, said columns of said non-volatile memory elements being divided into two sections so as to form first and second memory sections, said non-volatile memory elements of said first memory section being respectively paired with said non-volatile memory elements of said second memory section so as to form a plurality of memory cells for storing data bits, respectively; b) a plurality of word lines respectively coupled with said rows of said non-volatile memory elements, and selectively activating said memory cells; c) first digit lines respectively coupled with the columns of said non-volatile memory elements of said first memory section; d) second digit lines respectively coupled with the columns of said non-volatile memory elements of said second memory section, and respectively paired with said first digit lines so as to form digit line pairs for propagating data bits read out from activated memory cells, each of said data bits read out from said activated memory cells being in the form of a difference in voltage levels; e) a column selecting unit having first and second output nodes, and coupled wit said digit line pairs for interconnecting one of said digit line pairs and said first and second output nodes thereof; and f) a sensing amplifier unit comprising f-1) a first current mirror circuit coupled between a source of power voltage level and a first input node of said first current mirror circuit for allowing a first current to pass therebetween, and operative to control the amount of said first current, f-2) a first gate means responsive to the voltage level at said first output node, and relaying the voltage level at said first output node to said first input node, f-3) a second current mirror circuit coupled between said source of power voltage level and a second input node of said second current mirror circuit for allowing a second current to pass therethrough, and operative to control the amount of said second current, each of said first and second current mirror circuits comprising a first transistor with a first channel conductivity type coupled between a first source of voltage level and one of said first and second input nodes, and a second transistor with said second channel conductivity type coupled between said first source of voltage level and one of said third and fourth input nodes, said first and second transistors being gated from said one of said first and second input nodes f-4) a second gate means responsive to the voltage level at said second output node, and relaying the voltage level at said second output node to said second input node, each of said first and second gate means comprising an inverting circuit having an input node coupled to one of said first and second output nodes, and a gate transistor coupled between one of said first and second output nodes and one of said first and second input nodes and gated from said inverting circuit f-5) a third current mirror circuit having a first current path assigned to said first current, a second current path assigned to said second current, a third input node supplied with said first current for concurrently controlling the conductances of said first and second current paths, and a fourth input node supplied with said second current path, said first current path being formed by at least ninth and tenth transistors with a second channel conductivity type opposite to said first channel conductivity type coupled in parallel between said third input node and said ratio controlling circuit, said ninth and tenth transistors being gated from said third input node, f-6) an output inverting circuit having an input node coupled with said fourth input node and producing an output data signal, and f-7) a ratio controlling circuit responsive to said output data signal and operative to change a ratio of the conductance of said second current path to said conductance of said first current path.

Claim 10

A non-volatile semiconductor memory device fabricated on a single semiconductor chip as set forth in claim 5, in which said ratio controlling circuit comprises at least sixth, seventh and eighth transistors with said second channel conductivity type coupled between said third to fifth transistors and a second source of voltage level, said sixth and seventh transistors having respective gate electrodes coupled with said first source of voltage level, said eighth transistor being gated with said output data signal.

Claim 11

A non-volatile semiconductor memory device fabricated on a single semiconductor chip as set forth in claim 6, in which said second current path is formed by at least eleventh, twelfth, thirteenth and fourteenth transistors with said second channel conductivity type coupled in parallel between said fourth input node and said ratio controlling circuit, said eleventh to fourteenth transistors being gated by said third input node.

Claim 12

A non-volatile semiconductor memory device fabricated on a single semiconductor chip as set forth in claim 8, in which said ratio controlling circuit comprises at least fifteenth, sixteenth, seventeenth, eighteenth, nineteenth and twentieth transistors with said second channel conductivity type coupled in parallel between said fourth input node and a second source of voltage level, said fifteenth, sixteenth and seventeenth transistors having respective gate electrodes coupled with said first source of voltage level, said eighteenth, nineteenth and twentieth transistors being gated with said output data signal.