Semiconductor memory device

Claim 1

A semiconductor memory device with a redundant configuration wherein a spare memory cell is provided in addition to a normal memory cell, said semiconductor memory device comprising: a roll call circuit for outputting a first control signal of a first ECL level when a level of one of a read instruction signal and a write instruction signal is within a predetermined range, and wherein said first control signal is output at a second ECL level when said level of said write instruction signal is outside of the predetermined range, said roll call circuit further generating a second control signal of a second ECL level when said spare memory cell is selected; a sense amplifier responsive to said second control signal from said roll call circuit for outputting an output signal of a second ECL level when said second control signal received from said roll call circuit is at a second ECL level indicating that said spare memory cell is accessed; an output control circuit responsive to said first control signal from said roll call circuit for outputting a third control signal of one of the first ECL level and the second ECL level upon receipt of one of said read instruction signal and said write instruction signal when said first control signal received from said roll call circuit is at the first ECL level, and wherein said output control circuit outputs the third control signal of the first ECL level when said first control signal received from said roll call circuit is at the second ECL level; and an output buffer circuit for performing a logical NOR operation of said third control signal received from said output control circuit and said output signal received from said sense amplifier, and for generating a detection signal having the second ECL level which is supplied to an output terminal indicating that the spare memory cell is in use.