Patent US5266826A successfully refreshed from Google Patents.
US5266826A
Expired / Lapsed
US
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Semiconductor integrated circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1992-05-05
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Granted: 1993-11-30
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Expires: 2012-05-05
Abstract
Abstract Write transistors Q 1W , Q 2W , Q 3W , Q 4W are arranged in a line, and read transistors Q 1R , Q 2R , Q 3R , Q 4R are also arranged in a line. Wiring pads P11, P12, P13, P14 are arranged between the write and read transistors in a line parallel to both of the lines. Heat generated by a write operation in the write transistors does not significantly influence the read transistors in a read operation. The influences are exerted on the read transistors approximately uniformly, so that an offset voltage difference can be minimized in differential amplification.
Inventors
- 👤 Takehiko Umeyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:44
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H03; H03F; H03F3/00; H03F3/72; H10D; H10D89/00; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W40/00; H10W40/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
60 words
A semiconductor integrated circuit comprising a plurality of input/output circuits disposed adjacent to each other, each of said plurality of input/output circuits including a pair of input transistors for performing differential amplification, one or more wiring pads, and one or more output transistors disposed in opposite relation to said pair of input transistors across said one or more wiring pads.
Claim 2
Dependent Claim
60 words
A semiconductor integrated circuit comprising a plurality of input/output circuits disposed adjacent to each other, each of said plurality of input/output circuits including a pair of input transistors for performing differential amplification, one or more wiring pads, and one or more output transistors disposed in opposite relation to said pair of input transistors across said one or more wiring pads.
Claim 3
Dependent Claim
35 words
A semiconductor integrated circuit in accordance with claim 1, wherein said output transistors in operation have a relatively large heating value, and said pair of input transistors in operation have a relatively small heating value.
Claim 4
Dependent Claim
27 words
A semiconductor integrated circuit in accordance with claim 2, wherein said output transistors are magnetic write transistors, and said pair of input transistors are magnetic read transistors.
Claim 5
Dependent Claim
19 words
A semiconductor integrated circuit in accordance with claim 3, wherein said one or more output transistors are in plurality.
Claim 6
Dependent Claim
19 words
A semiconductor integrated circuit in accordance with claim 4, wherein said one or more output transistors are in pairs.
Claim 7
Dependent Claim
26 words
A semiconductor integrated circuit in accordance with claim 4, wherein said one or more wiring pads are equal in number to said plurality of output transistors.
Claim 8
Dependent Claim
56 words
A semiconductor integrated circuit in accordance with claim 6, wherein said output transistors in plurality are arranged in a first row, said wiring pads in plurality are arranged in a second row parallel to said first row, and said pair of input transistors are arranged in a third row parallel to said first and second rows.
Claim 9
Dependent Claim
72 words
A semiconductor integrated circuit in accordance with claim 7, wherein said plurality of input/output circuits include first and second input/output circuits, said output transistors in said first and second input/output circuits are arranged in said first row, said wiring pads in said first and second input/output circuits are arranged in said second row, and said pair of input transistors in said first and second input/output circuits are arranged in said third row.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-29 | 1997-05-31 | 1997-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-29 | 2001-05-31 | 2001-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-29 | 2005-05-31 | 2005-11-30 | $7700.00 | Window Closed / Lapsed |