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US5266824A Expired / Lapsed US ⏱️ 0.0 years remaining

SOI semiconductor substrate

Assignee: Shin-Etsu Handotai Co Ltd
•
Filing: 1992-03-16
•
Granted: 1993-11-30
•
Expires: 2012-03-16
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Abstract

Abstract The present invention provides a semiconductor substrate which is formed by bonding wafers together by heat treatment without causing the substrate to be thermally damaged to have thermal strain, separation, cracks, etc. due to the difference in the thermal expansion coefficient of the wafers, and particularly a semiconductor substrate having an SOI structure which can provide a silicon film thin enough to allow various integrated circuits or TFT-LCD to be formed In the present invention, after wafers are bonded temporarily in a low temperature range, one of the wafers is made thin by chemical treatment, then the wafers were bonded fully by heat treatment in a temperature range (where the thermal expansion coefficient of the wafer are not affected) higher than the above low temperature range, and then said one wafer can be made thinner by mechanical grinding or polishing mechano-chemically. Thus according to the present invention, even if a semiconductor substrate is formed by sticking a silicon wafer and a quartz wafer together, damages that will be caused thermally due to thermal expansion can be prevented and a film which is made thin enough required for forming various integrated circuits or TFT-LCD or the like can be easily obtained.

Inventors

  • 👤 Takao Abe
  • 👤 Yasuaki Nakazato
  • 👤 Atsuo Uchiyama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 15:06
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454; Y; Y10; Y10S; Y10S438/00; Y10S438/977

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 133 words
A semiconductor substrate comprising a quartz wafer and a second water of material other than quartz having a predetermined initial thickness, said quartz wafer and said second wafer having different thermal expansion coefficients, said quartz wafer and said second wafer having polished and cleaned surfaces temporarily bonded to each other by pressing against each other and heating in a first temperature range, said second wafer being reduced in thickness by chemical treatment to a thickness less than said predetermined initial thickness and thereafter more strongly bonded to said quartz wafer without thermal damage due to the differing thermal expansion coefficients by heating in a second temperature range higher than said first temperature range to effect bonding sufficient to withstand grinding stresses, and said second wafer having a mechano-chemically polished exposed surface formed thereon.
Claim 2
Dependent Claim 133 words
A semiconductor substrate comprising a quartz wafer and a second water of material other than quartz having a predetermined initial thickness, said quartz wafer and said second wafer having different thermal expansion coefficients, said quartz wafer and said second wafer having polished and cleaned surfaces temporarily bonded to each other by pressing against each other and heating in a first temperature range, said second wafer being reduced in thickness by chemical treatment to a thickness less than said predetermined initial thickness and thereafter more strongly bonded to said quartz wafer without thermal damage due to the differing thermal expansion coefficients by heating in a second temperature range higher than said first temperature range to effect bonding sufficient to withstand grinding stresses, and said second wafer having a mechano-chemically polished exposed surface formed thereon.
Claim 3
Dependent Claim 73 words
A semiconductor substrate according to claim 1, wherein said substrate is produced by a process further comprising subjecting said second wafer, after it is more strongly bonded to said quartz wafer, to chemical or mechanical treatment to further reduce the thickness of said second wafer, and heat treating said substrate in a third temperature range higher than said second temperature range prior to forming said mechano-chemically polished exposed surface on said second wafer.
Claim 4
Dependent Claim 28 words
A semiconductor substrate according to claim 1, wherein said chemical treatment to reduce the thickness of said second wafer is effected by etching with an aqueous alkali solution.
Claim 5
Dependent Claim 15 words
A semiconductor substrate according to claim 1, wherein said second wafer is a silicon wafer.
Claim 6
Dependent Claim 74 words
A semiconductor substrate according to claim 1, wherein said second wafer has an initial thickness in the range from 500 to 600 μm, said chemical treatment reduces the thickness of said second wafer to a thickness in the range from 100 to 200 μm, and after heating in said second temperature range, said second wafer is ground to a thickness of about 20 μm and polished to a final thickness of about 2 μm.
Claim 7
Dependent Claim 31 words
A semiconductor substrate according to claim 1, wherein said first temperature range is from about 110° to 350° C., and said second temperature range is from about 350° to 500° C.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-11-29 1997-05-31 1997-11-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-11-29 2001-05-31 2001-11-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-11-29 2005-05-31 2005-11-30 $7700.00 Window Closed / Lapsed

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