Signal detection apparatus for detecting digital information from PCM signal

Claim 2

A signal detection apparatus for detecting digital information from a PCM signal transmitted through a communication channel or reproduced from a recording medium, comprising: a first equalizing means for equalizing the PCM signal so as to decrease intersymbol interferences; a clock regenerating means comprising a phase locked loop circuit for regenerating a clock signal synchronized with an output signal of the first equalizing means from a phase of a zero-crossing point of the output signal of the first equalizing means; a second equalizing means for subjecting the output signal of the first equalizing means to partial-response equalization so as to cause a specific intersymbol interference to obtain a partial-response equalized signal; an amplitude detecting means responsive to the clock signal for detecting an amplitude of the output signal of the first equalizing means at a clock timing of the clock signal; and a detecting means responsive to the clock signal for comparing the partial-response equalized signal outputted from the second equalizing means with the amplitude detected by the amplitude detecting means at the clock timing of the clock signal to obtain the digital information.

Claim 3

An apparatus according to claim 1, wherein the amplitude detecting means comprises a sampling means for sampling the output signal of the first equalizing means at the clock timing of the clock signal, and an absolute value means for obtaining an absolute value of an output of the sampling means, and a smoothing means for smoothing an output of the absolute value means.

Claim 4

A signal detection apparatus for detecting digital information from PCM signal transmitted through a communication channel or reproduced from a recording medium, comprising: a first equalizing means for equalizing the PCM signal so as to decrease intersymbol interferences; a clock regenerating means comprising a phase locked loop circuit for regenerating a clock signal synchronized with an output signal of the first equalizing means from a phase of a zero-crossing point of the output signal of the first equalizing means; an analog-to-digital converting means responsive to the clock signal for sampling and quantizing the output signal of the equalizing means at a clock timing of the clock signal; a second equalizing means for subjecting an output signal of the analog-to-digital converting means in a form of a digital signal to partial-response equalization so as to cause a specific intersymbol interference to obtain a partial-response equalized signal; an amplitude detecting means for detecting an amplitude of the output signal of the analog-to-digital converting means; and a detecting means for comparing the partial-response equalized signal outputted from the second equalizing means with the amplitude detected by the amplitude detecting means to obtain the digital information.

Claim 5

A signal detection apparatus for detecting digital information from PCM signal transmitted through a communication channel or reproduced from a recording medium, comprising: a first equalizing means for equalizing the PCM signal so as to decrease intersymbol interferences; a clock regenerating means comprising a phase locked loop circuit for regenerating a clock signal synchronized with an output signal of the first equalizing means from a phase of a zero-crossing point of the output signal of the first equalizing means; an analog-to-digital converting means responsive to the clock signal for sampling and quantizing the output signal of the equalizing means at a clock timing of the clock signal; a second equalizing means for subjecting an output signal of the analog-to-digital converting means in a form of a digital signal to partial-response equalization so as to cause a specific intersymbol interference to obtain a partial-response equalized signal; an amplitude detecting means for detecting an amplitude of the output signal of the analog-to-digital converting means; and a detecting means for comparing the partial-response equalized signal outputted from the second equalizing means with the amplitude detected by the amplitude detecting means to obtain the digital information.

Claim 6

An apparatus according to claim 3, wherein the amplitude detecting means comprises an absolute value means for obtaining an absolute value of the output signal of the analog-to-digital converting means, and a smoothing means for smoothing an output signal of the absolute value means.

Claim 7

A signal detection apparatus for detecting digital information from a PCM signal transmitted through a communication channel or reproduced from a recording medium, comprising: a first equalizing means for equalizing the PCM signal so as to decrease intersymbol interferences; a clock regenerating means comprising a phase locked loop circuit for regenerating a clock signal synchronized with an output signal of the first equalizing means from a phase of a zero-crossing point of the output signal of the first equalizing means; an analog-to-digital converting means responsive to the clock signal for sampling and quantizing the output signal of the equalizing means at a clock timing of the clock signal; a second equalizing means for subjecting an output signal of the analog-to-digital converting means in a form of a digital signal to partial-response equalization so as to cause a specific intersymbol interference to obtain a partial-response equalized signal; an amplitude detecting means for detecting an amplitude of the output signal of the analog-to-digital converting means; and a Viterbi decoder for estimating a maximum likelihood of a state transition determined by partial-response equalization from the partial-response equalized signal outputted from the second equalizing means and the amplitude detected by the amplitude detecting means to detect the digital information.

Claim 8

A signal detection apparatus for detecting digital information from a PCM signal transmitted through a communication channel or reproduced from a recording medium, comprising: a first equalizing means for equalizing the PCM signal so as to decrease intersymbol interferences; a clock regenerating means comprising a phase locked loop circuit for regenerating a clock signal synchronized with an output signal of the first equalizing means from a phase of a zero-crossing point of the output signal of the first equalizing means; an analog-to-digital converting means responsive to the clock signal for sampling and quantizing the output signal of the equalizing means at a clock timing of the clock signal; a second equalizing means for subjecting an output signal of the analog-to-digital converting means in a form of a digital signal to partial-response equalization so as to cause a specific intersymbol interference to obtain a partial-response equalized signal; an amplitude detecting means for detecting an amplitude of the output signal of the analog-to-digital converting means; and a Viterbi decoder for estimating a maximum likelihood of a state transition determined by partial-response equalization from the partial-response equalized signal outputted from the second equalizing means and the amplitude detected by the amplitude detecting means to detect the digital information.

Claim 9

An apparatus according to claim 5, wherein the amplitude detecting means comprises an absolute value means for obtaining an absolute value of the output signal of the analog-to-digital converting means, and a smoothing means for smoothing an output signal of the absolute value means.