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US5265101A
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Function array sequencing for VLSI test system
Assignee: Texas Instruments Inc
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Filing: 1989-04-12
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Granted: 1993-11-23
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Expires: 2009-04-12
Abstract
Abstract A function array system includes a controller, a test function and specific memories to accelerate the execution of a VLSI device test program by preloading register files associate with each hardware function in the tester with test set-up information. Test information is transferred to the register files only once when the test program is initially downloaded into the tester. A simple controller sequences a test set-up pointer during test execution.
Inventors
- 👤 Marc R. Mydill
- 👤 Mark E. Carlson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
92 words
A test system for testing integrated circuits with a plurality of tests, comprising: a central controller for selecting a test to be performed from among said plurality of tests; a plurality of function generators operating in parallel to carry out the selected test; pin electronics for applying test parameters to the integrated circuits under test; a set up address bus divided into function groups, wherein one of said function groups may be changed without affecting the other function groups; and setup registers for controlling which of said function groups may be changed.
Claim 2
Dependent Claim
92 words
A test system for testing integrated circuits with a plurality of tests, comprising: a central controller for selecting a test to be performed from among said plurality of tests; a plurality of function generators operating in parallel to carry out the selected test; pin electronics for applying test parameters to the integrated circuits under test; a set up address bus divided into function groups, wherein one of said function groups may be changed without affecting the other function groups; and setup registers for controlling which of said function groups may be changed.
Claim 3
Dependent Claim
24 words
The test system according to claim 1, wherein the pine electronics are the functional and AC test interface to the integrated circuit under test.
Claim 4
Dependent Claim
59 words
The test system according to claim 1, including test setup memory registers, each test setup memory register including a plurality of register locations, each location storing a function value associated with a different test procedure, the function value being used to program one of said plurality of function generators associated with each one of said test setup memory registers.
Claim 5
Dependent Claim
22 words
The test system according to claim 1, wherein the function groups include pin electronics, a DC test subsystem and a relay matrix.
Claim 6
Dependent Claim
29 words
The test system according to claim 4, including a setup address register for each function group allowing the changing of tester function of one function group without changing others.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |