US5264712A
Expired / Lapsed
US
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Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
Assignee: Rising Silicon Inc
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Filing: 1992-05-07
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Granted: 1993-11-23
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Expires: 2012-05-07
Abstract
Abstract A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
Inventors
- 👤 Jun Murata
- 👤 Yoshitaka Tadaki
- 👤 Hiroko Kaneko
- 👤 Toshihiro Sekiguchi
- 👤 Hiroyuki Uchiyama
- 👤 Hisashi Nakamura
- 👤 Toshio Maeda
- 👤 Osamu Kasahara
- 👤 Hiromichi Enami
- 👤 Atsushi Ogishima
- 👤 Masaki Nagao
- 👤 Michimasa Funabashi
- 👤 Yasuo Kiguchi
- 👤 Masayuki Kojima
- 👤 Atsuyoshi Koike
- 👤 Hiroyuki Miyazawa
- 👤 Masato Sadaoka
- 👤 Kazuya Kadota
- 👤 Tadashi Chikahara
- 👤 Kazuo Nojiri
- 👤 Yutaka Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:29
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/50; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/0133; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
479 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface, said main surface including a first potion, a second portion and a third portion between said first and second portions; a first memory array formed at said first portion of said main surface of said semiconductor substrate, and a second memory array formed at said second portion of said main surface of said semiconductor substrate, and said first and second memory array being adjacent with each other, wherein each of said first and second memory arrays includes: memory cells arranged in row and column directions, each of memory cells having a MOSFET and a capacitor element coupled in series, said MOSFET having a gate electrode, source region and drain region, and said capacitor element having a first electrode coupled to one of said source and drain regions, a second electrode and a dielectric layer between said first and second electrodes, wherein said second electrode extended over said gate of said MOSFET; parallel first word lines extending in said row direction from aid first portion to said second portion contiguously and each being unitary with said gate electrodes of said MOSFETs in said memory cells arranged in the row direction in said first and second memory arrays; parallel data lines extending in the column direction and each connected to the other of source an drain regions of memory cells arranged in the column direction in said first and second memory arrays; parallel second word liens extending in the row direction from said first portion to said second portion continuously and each being over said second electrodes of said capacitors provided in said first and second memory arrays, said second word lines comprising a conductive layer having lower resistivity than that of said first word lines; an inner-layer conductive layer formed at said third portion of said main surface of semiconductor substrate, said inlayer conductive layer electrically connecting each of said first word lines to each of said second word lines; a first insulating film formed between said first word lines and said inter-layer conductive layer at said third portion of said main surface of said semiconductor substrate, said first insulating film having a first connecting hole so as to provide electrical connection between said each of said word lines and said inner-layer conducive layer; and a second insulating film formed between said inter-layer conductive layer and said second word lines at said third portion of said main surface of said semiconductor substrate, said second insulating film having a second connecting hole so as to provide electrical connection between said inter-layer conducive layer and said each of second word lines, wherein said second electrode of at least one of said capacitor elements continuously extends from said first portion to said third portion, and said second connecting hole is over said at least one second electrode at said third portion.
Claim 2
Dependent Claim
479 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface, said main surface including a first potion, a second portion and a third portion between said first and second portions; a first memory array formed at said first portion of said main surface of said semiconductor substrate, and a second memory array formed at said second portion of said main surface of said semiconductor substrate, and said first and second memory array being adjacent with each other, wherein each of said first and second memory arrays includes: memory cells arranged in row and column directions, each of memory cells having a MOSFET and a capacitor element coupled in series, said MOSFET having a gate electrode, source region and drain region, and said capacitor element having a first electrode coupled to one of said source and drain regions, a second electrode and a dielectric layer between said first and second electrodes, wherein said second electrode extended over said gate of said MOSFET; parallel first word lines extending in said row direction from aid first portion to said second portion contiguously and each being unitary with said gate electrodes of said MOSFETs in said memory cells arranged in the row direction in said first and second memory arrays; parallel data lines extending in the column direction and each connected to the other of source an drain regions of memory cells arranged in the column direction in said first and second memory arrays; parallel second word liens extending in the row direction from said first portion to said second portion continuously and each being over said second electrodes of said capacitors provided in said first and second memory arrays, said second word lines comprising a conductive layer having lower resistivity than that of said first word lines; an inner-layer conductive layer formed at said third portion of said main surface of semiconductor substrate, said inlayer conductive layer electrically connecting each of said first word lines to each of said second word lines; a first insulating film formed between said first word lines and said inter-layer conductive layer at said third portion of said main surface of said semiconductor substrate, said first insulating film having a first connecting hole so as to provide electrical connection between said each of said word lines and said inner-layer conducive layer; and a second insulating film formed between said inter-layer conductive layer and said second word lines at said third portion of said main surface of said semiconductor substrate, said second insulating film having a second connecting hole so as to provide electrical connection between said inter-layer conducive layer and said each of second word lines, wherein said second electrode of at least one of said capacitor elements continuously extends from said first portion to said third portion, and said second connecting hole is over said at least one second electrode at said third portion.
Claim 3
Dependent Claim
29 words
A semiconductor memory device according to claim 1, further comprising a field insulating film formed at said third portion, said first word line extending over said field insulating film.
Claim 4
Dependent Claim
17 words
A semiconductor memory device according to claim 2, wherein said field insulating film is silicon oxide film.
Claim 5
Dependent Claim
24 words
A semiconductor memory device according to claim 2, wherein said first and second electrodes of said capacitor element are comprised of polycrystalline silicon films.
Claim 6
Dependent Claim
24 words
A semiconductor memory device according to claim 2, wherein a fixed potential is supplied to said second electrode of each of is capacitor elements.
Claim 7
Dependent Claim
28 words
A semiconductor memory device according to claim 5, wherein said second electrodes of said capacitor elements in said first and second memory array are unitary with each other.
Claim 8
Dependent Claim
46 words
A semiconductor memory device according to claim 6, further comprising a wiring extending along said first memory array in said column direction and at said third portion, said wiring being connected to said second electrode of said capacitor element so as to supply said fixed potential.
Claim 9
Dependent Claim
41 words
A semiconductor memory device according to claim 6, wherein said second electrode has holes at said third portion so that said first connecting hole formed in said first insulating film is formed in said each of holes of said second electrode.
Claim 10
Dependent Claim
19 words
A semiconductor memory device according to claim 1, wherein said row and column directions are perpendicular to one another.
Claim 11
Dependent Claim
29 words
A semiconductor memory device according to claim 1, wherein each of said capacitor elements is a vertically stacked capacitor wherein said second electrode is formed over said first electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |