Microprocessor with an exclusive address terminal for selecting at least one part of a peripheral device

Claim 2

A digital electronic circuit device comprising: central processing means having plural terminals including a multiplexed address/data terminal capable of outputting an address signal and a data signal in a time-sharing manner, an exclusive address terminal for addressing a one of a plurality of ports of a peripheral device, and an internal memory means for storing required data, said required data comprising a complete program, for said central processing means, wherein there is no requirement to output an address signal through said multiplexed address/data terminal; peripheral means for receiving at least one of said address signal and data signal from said central processing means, said peripheral means having a data terminal and an input terminal, an operational state of said peripheral means being changed in response to a signal inputted through said input terminal; first means for connecting said multiplexed terminal with said data terminal; and second means for connecting said input terminal with a terminal of said plural terminals of said central processing means other than said multiplexed terminal.

Claim 3

A digital electronic circuit device according to claim 1, wherein said central processing means has an address terminal for exclusively outputting an address signal, and said second means connects said input terminal of said peripheral means with said address terminal of said central processing means.

Claim 4

A digital electronic circuit device according to claim 1, wherein said peripheral means has plural ports one of which is selected in response to a signal inputted through said input terminal.

Claim 5

A digital electronic circuit device according to claim 1, further comprising: address latch means connected with said first means for temporarily storing an address signal supplied from said multiplexed terminal through said first means; external memory means, connected with said first means and addressed by said address signal stored in said address latch means, for supplying a data signal to said first means; and said address latch being responsive to an enabling signal output by said central processing means, said enabling signal also being input to a chip select terminal of said peripheral means.

Claim 6

A digital electronic circuit device according to claim 4, wherein said external memory means is detachably connected with both said address latch means and said first means by connector means.

Claim 7

A digital electronic circuit device comprising: a central processing means having plural terminal portions including a multiplexed address/data terminal portion capable of outputting and receiving address signals and data signals in a time-sharing manner and an output terminal portion provided independently of said multiplexed terminal portion wherein said output terminal portion is an address terminal for exclusively outputting address signals to at least one of a plurality of ports of a peripheral device in accordance with a complete program having required data for said central processing means, said complete program being stored in an internal memory means; peripheral means for receiving at least one of said address signals and data signals from said central processing means, said peripheral means having a data terminal portion and an input terminal portion, an operational state of said peripheral means being selected among plural predetermined states in response to signals inputted through said input terminal portion; first signal transferring means for connecting said multiplexed terminal portion to said data terminal portion; and second signal transferring means for connecting said output terminal portion to said input terminal portion.

Claim 8

A digital electronic circuit device comprising: a central processing means having plural terminal portions including a multiplexed address/data terminal portion capable of outputting and receiving address signals and data signals in a time-sharing manner and an output terminal portion provided independently of said multiplexed terminal portion wherein said output terminal portion is an address terminal for exclusively outputting address signals to at least one of a plurality of ports of a peripheral device in accordance with a complete program having required data for said central processing means, said complete program being stored in an internal memory means; peripheral means for receiving at least one of said address signals and data signals from said central processing means, said peripheral means having a data terminal portion and an input terminal portion, an operational state of said peripheral means being selected among plural predetermined states in response to signals inputted through said input terminal portion; first signal transferring means for connecting said multiplexed terminal portion to said data terminal portion; and second signal transferring means for connecting said output terminal portion to said input terminal portion.

Claim 9

A digital electronic circuit device comprising: a central processing means having a mulitplexed address/data terminal portion, an address terminal portion, said multiplexed address/data terminal portion being capable of outputting and receiving address signals and data signals in a time-sharing manner, said address terminal portion exclusively outputting address signals to at least one of a plurality of ports of a peripheral device, and an internal memory means for storing required data, said required data comprising a complete program for said central processing unit, wherein there is no requirement to output an address signal through said multiplexed address data terminal; a peripheral element for receiving at least one of said address signals and data signals from said central processing unit, said peripheral element having a data terminal portion, an input terminal portion and plural input/output ports, one of said plural input/output ports being selected in response to signals inputted through said input terminal portion; a multiplexed address/data bus for connecting said multiplexed address/data terminal portion with said data terminal portion; and an address bus for connecting said address terminal portion with said input terminal portion.

Claim 10

A digital electronic circuit device comprising: a central processing means having a mulitplexed address/data terminal portion, an address terminal portion, said multiplexed address/data terminal portion being capable of outputting and receiving address signals and data signals in a time-sharing manner, said address terminal portion exclusively outputting address signals to at least one of a plurality of ports of a peripheral device, and an internal memory means for storing required data, said required data comprising a complete program for said central processing unit, wherein there is no requirement to output an address signal through said multiplexed address data terminal; a peripheral element for receiving at least one of said address signals and data signals from said central processing unit, said peripheral element having a data terminal portion, an input terminal portion and plural input/output ports, one of said plural input/output ports being selected in response to signals inputted through said input terminal portion; a multiplexed address/data bus for connecting said multiplexed address/data terminal portion with said data terminal portion; and an address bus for connecting said address terminal portion with said input terminal portion.

Claim 11

A digital electronic circuit device according to claim 7, further comprising: an address latch connected with said multiplexed address/data bus for temporarily storing address signals supplied through said multiplexed address/data bus; an external memory addressed by said address signals stored in said address latch, said external memory being connected with said multiplexed address/data bus for supplying data signals to said central processing unit through said multiplexed address/data bus; and said address latch being responsive to an enabling signal output by said central processing means, said enabling signal also being input to a chip select terminal of said peripheral means.

Claim 12

A digital electronic circuit device according to claim 8, wherein said external memory is detachably connected with both said multiplexed address/data bus and said address latch by a connector.

Claim 13

A digital electronic circuit device comprising: central processing means having plural terminals including a multiplexed address/data terminal capable of outputting and receiving an address signal and a data signal in a time-sharing manner wherein at least one of said plural terminals is an address terminal provided independently of said multiplexed terminal for exclusively outputting an address signal to at least one of a plurality of ports of a peripheral device; peripheral means for receiving at least one of said address signal and data signal from said central processing means, said peripheral means having a data terminal and an input terminal, an operational state of said peripheral means being changed in response to a signal inputted through said input terminal; first means for connecting said multiplexed terminal with said data terminal; address latch means connected with said first means for receiving an address signal from said multiplexed terminal through said first means; external memory means connected with said first means for supplying a data signal to said central processing means, said external memory being addressed by said address signal stored in said address latch means; and second means for connecting said input terminal with a terminal of said plural terminals of said central processing means other than said multiplexed terminals.

Claim 14

A digital electronic circuit device comprising: central processing means having plural terminals including a multiplexed address/data terminal capable of outputting and receiving an address signal and a data signal in a time-sharing manner wherein at least one of said plural terminals is an address terminal provided independently of said multiplexed terminal for exclusively outputting an address signal to at least one of a plurality of ports of a peripheral device; peripheral means for receiving at least one of said address signal and data signal from said central processing means, said peripheral means having a data terminal and an input terminal, an operational state of said peripheral means being changed in response to a signal inputted through said input terminal; first means for connecting said multiplexed terminal with said data terminal; address latch means connected with said first means for receiving an address signal from said multiplexed terminal through said first means; external memory means connected with said first means for supplying a data signal to said central processing means, said external memory being addressed by said address signal stored in said address latch means; and second means for connecting said input terminal with a terminal of said plural terminals of said central processing means other than said multiplexed terminals.

Claim 15

A digital electronic circuit device according to claim 10, wherein said second means connects said input terminal of said peripheral means with said address terminal.

Claim 16

A digital electronic circuit device according to claim 10, wherein said external memory means is detachably connected with both said first means and said address latch by connector means.