Justification decision circuit for an arrangement for bit rate adjustment

Claim 1

A circuit for adjusting the bit rate of two plesiochronous signals, comprising: memory for storing data of a first signal in parallel in groups of n bits each, means for reading out the data stored in said groups and inserting stuff bits at predetermined locations, a write counter for controlling writing of said data in said memory, a read counter for controlling reading out of said memory, and a justification decision circuit for controlling said means for reading out, said justification decision circuit including a controller and a subtractor, said subtractor having an output which is the difference between the counts of the read and write counters, said subtractor, controller and read counter forming a control loop, characterized in that said controller comprises a mean value determining circuit for determining a mean value of said subtractor output, a track counter, and means for offsetting a magnitude value proportional to said mean value, said mean value determining circuit determining the mean value of the subtractor output over a predetermined time interval, said track counter being arranged for counting modulo n said stuffed bits, and providing a read stop signal for one clock period after each n stuffed bits, said controller further comprising means for stopping said read counter for one block period responsive to said read stop signal, and said mean for offsetting using the result of the offset as a preparation signal for incrementing the track counter.

Claim 8

A method of adjusting the bit rate of two plesiochronous signals, comprising: storing data of a first signal in parallel in groups of n bits each in a memory, counting read bits and reading out the data stored in said groups and inserting stuff bits at predetermined locations according to a read count, counting write clock bits and controlling writing of said data in said memory according to a write count, forming a difference value which is the difference between said read and write counts, and responsive to a function of said difference value, controlling insertion of said stuff bits, characterized by the steps of: determining a mean value of said difference value over a predetermined time interval, counting modulo n the inserted stuff bits to form a track count, and providing a read stop signal for one clock period after each n stuffed bits, determining a magnitude value proportional to said mean value, and offsetting said magnitude value against said track count, stopping said read counter for one clock period responsive to said read stop signal, and using the result of the offset as a preparation signal for incrementing the modulo n count of said stuffed bits.

Claim 9

A method of adjusting the bit rate of two plesiochronous signals, comprising: storing data of a first signal in parallel in groups of n bits each in a memory, counting read bits and reading out the data stored in said groups and inserting stuff bits at predetermined locations according to a read count, counting write clock bits and controlling writing of said data in said memory according to a write count, forming a difference value which is the difference between said read and write counts, and responsive to a function of said difference value, controlling insertion of said stuff bits, characterized by the steps of: determining a mean value of said difference value over a predetermined time interval, counting modulo n the inserted stuff bits to form a track count, and providing a read stop signal for one clock period after each n stuffed bits, determining a magnitude value proportional to said mean value, and offsetting said magnitude value against said track count, stopping said read counter for one clock period responsive to said read stop signal, and using the result of the offset as a preparation signal for incrementing the modulo n count of said stuffed bits.