Spline-wavelet signal analyzers and methods for processing signals

Claim 2

A signal processor, comprising: means for receiving an analog signal; means for sampling the analog signal at a predetermined sampling period to produce a plurality of discrete signal samples; means for digitizing the discrete signal samples to produce a plurality of digital signal samples; means for generating a plurality of spline coefficients of the zero level in response to receiving the digital signal sample, said means for generating including means for multiplying a plurality of predetermined stored weights to respective selected ones of the digitized signal samples and means for summing the weighted digitized signal samples together in a moving average operation to derive zeroth-level B-spline coefficients; means for multiplying the zeroth-level B-spline coefficients in a moving average operation by a plurality of a n -constants to derive a plurality of first-level B-spline coefficients for the signal; means for multiplying the zeroth-level B-spline coefficients in a moving average operation by a plurality of b n -constants to derive a plurality of first-level wavelet coefficients; means for generating at least one spline function from at least one respective set of spline coefficients; and means for generating at least one wavelet function from at least one respective set of wavelet coefficients whereby the analog signal is processed for analyzing frequency information of the analog signal.

Claim 3

The signal processor of claim 1, and further comprising: S additional processor stages, where S≧1, each said stage comprising for the xth additional stage (xε1..S): means for multiplying the x-level spline coefficients in a moving average operation by said plurality of a n -constants to derive a plurality of (x+1)-level spline coefficients; means for multiplying the x-level spline coefficients in a moving average operation by said plurality of b n -constants to derive a plurality of (x+1)-level wavelet coefficients; means for generating the (x+1)-level spline function from the (x+1)-level spline coefficients; and means for generating the (x+1)-level wavelet function from the (x+1)-level wavelet coefficients.

Claim 4

The signal processor of claim 1, wherein said means for generating at least one spline function comprises: means for storing parameters of a spline precursor waveform; means for multiplying a selected string of the spline coefficients by the parameters of spline precursor waveform; means for summing the multiplied parameters of spline precursor waveform with portions of prior parameters of spline precursor waveforms derived from prior spline coefficient strings to produce an intermediate signal; means for integrating the intermediate signal a number of times equal to the order of spline sought to be generated minus one; and means for outputting the integrated intermediate signal as the spline function.

Claim 5

The signal processor of claim 3, and further comprising, for each said means for integrating, a buffer coupled to an output of said means for integrating.

Claim 6

The signal processor of claim 3, wherein said spline precursor waveform comprises a step function of finite length.

Claim 7

The signal processor of claim 1, wherein said means for generating at least one wavelet function comprises: means for storing parameters of a wavelet precursor waveform; means for multiplying a selected string of the wavelet coefficients by the parameters of wavelet precursor waveform; means for summing the multiplied parameters with portions of prior multiplied parameters derived from prior wavelet coefficient strings to produce an intermediate signal; means for integrating the intermediate signal a number of times equal to the order of wavelet sought to be generated; and means for outputting the integrated intermediate signal as the wavelet function.

Claim 8

The signal processor of claim 6, wherein said means for integrating has an output, a buffer coupled to said output of said means for integrating.

Claim 9

The signal processor of claim 6, wherein said wavelet precursor waveform comprises a step function of finite length.

Claim 10

A linear spline function generator, comprising: a memory for storing parameters of a spline precursor function, said parameters preselected such that an analog signal based thereon, when integrated, will yield a linear B-spline; a multiplier, a first port of said multiplier receiving said parameters of said spline precursor function, a second port of said multiplier receiving a string of spline coefficients, an output of said multiplier outputting a plurality of current sets of multiplied parameters in response to receiving said parameters of said spline precursor function and said string of spline coefficients; a summer for summing said current multiplied parameters with stored prior multiplied precursor parameters and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving said intermediate sequence and an output port for outputting an intermediate signal; an integrator having an input port for receiving said intermediate signal and an output port, an integrated intermediate signal appearing at said output port in response to the receipt of said intermediate signal at said input port of said integrator; and a buffer having an input port coupled to said output port of said integrator, said linear spline function appearing at said output port of said buffer in response to said integrated intermediate signal being received at said input port thereof.

Claim 11

A linear spline function generator, comprising: a memory for storing parameters of a spline precursor function, said parameters preselected such that an analog signal based thereon, when integrated, will yield a linear B-spline; a multiplier, a first port of said multiplier receiving said parameters of said spline precursor function, a second port of said multiplier receiving a string of spline coefficients, an output of said multiplier outputting a plurality of current sets of multiplied parameters in response to receiving said parameters of said spline precursor function and said string of spline coefficients; a summer for summing said current multiplied parameters with stored prior multiplied precursor parameters and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving said intermediate sequence and an output port for outputting an intermediate signal; an integrator having an input port for receiving said intermediate signal and an output port, an integrated intermediate signal appearing at said output port in response to the receipt of said intermediate signal at said input port of said integrator; and a buffer having an input port coupled to said output port of said integrator, said linear spline function appearing at said output port of said buffer in response to said integrated intermediate signal being received at said input port thereof.

Claim 12

The generator of claim 9, wherein said spline function is a step function of finite length.

Claim 13

A linear spline wavelet function generator, comprising: a memory for storing parameters of a spline wavelet precursor function, said parameters preselected such that an analog signal based thereon, when integrated, will yield a linear B-wavelet; a multiplier, a first port of said multiplier receiving said parameters, a second port of said multiplier receiving a string of wavelet coefficients, an output of said multiplier outputting a plurality of current sets of multiplied parameters in response to receiving said parameters and said string of wavelet coefficients; a summer for summing said current multiplied parameters with stored prior multiplied precursor parameters and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving said intermediate sequence and an output port for outputting an intermediate signal; an integrator having an input port for receiving said intermediate signal and an output port, an integrated intermediate signal appearing at said output port in response to the receipt of said intermediate signal at said input port of said integrator; and a buffer having an input port coupled to said output port of said integrator and an output port, said linear wavelet function appearing at said output port of said buffer in response to said integrated intermediate signal being received at said input port thereof.

Claim 14

A linear spline wavelet function generator, comprising: a memory for storing parameters of a spline wavelet precursor function, said parameters preselected such that an analog signal based thereon, when integrated, will yield a linear B-wavelet; a multiplier, a first port of said multiplier receiving said parameters, a second port of said multiplier receiving a string of wavelet coefficients, an output of said multiplier outputting a plurality of current sets of multiplied parameters in response to receiving said parameters and said string of wavelet coefficients; a summer for summing said current multiplied parameters with stored prior multiplied precursor parameters and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving said intermediate sequence and an output port for outputting an intermediate signal; an integrator having an input port for receiving said intermediate signal and an output port, an integrated intermediate signal appearing at said output port in response to the receipt of said intermediate signal at said input port of said integrator; and a buffer having an input port coupled to said output port of said integrator and an output port, said linear wavelet function appearing at said output port of said buffer in response to said integrated intermediate signal being received at said input port thereof.

Claim 15

The generator of claim 11, wherein said spline wavelet precursor function is a step function of finite length.

Claim 16

A wavelet generator for generating an mth order wavelet function of a sequence, comprising: a memory for storing parameters of a B-wavelet precursor function which, when passed-through a digital to analog converter and integrated (m-1) times and buffered (m-1) times, will yield a B-wavelet of the mth order; a multiplier, a first port of said multiplier receiving said B-wavelet precursor parameters, a second port of said multiplier receiving a string of wavelet coefficients derived from said signal, an output of said multiplier outputting a plurality of current multiplied precursor parameters in response to receiving said B-wavelet precursor parameters and said string of wavelet coefficients; a summer for summing said current multiplied precursor parameters with stored prior multiplied precursor function wavelet elements and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving the said intermediate sequence and an output port for outputting an intermediate signal; and (m-1) integrating and buffering stages, each of said integrating and buffering stages comprising an integrator having an input port and an output and a buffer having an input coupled to said output of said integrator and an output port thereof, said input port of a first of said integrating and buffering stages operable to receive said intermediate signal, said mth order wavelet function of said signal appearing at said output port of a last of said integrating and buffering stages in response to said input port of said first stage receiving said intermediate signal.

Claim 17

A wavelet generator for generating an mth order wavelet function of a sequence, comprising: a memory for storing parameters of a B-wavelet precursor function which, when passed-through a digital to analog converter and integrated (m-1) times and buffered (m-1) times, will yield a B-wavelet of the mth order; a multiplier, a first port of said multiplier receiving said B-wavelet precursor parameters, a second port of said multiplier receiving a string of wavelet coefficients derived from said signal, an output of said multiplier outputting a plurality of current multiplied precursor parameters in response to receiving said B-wavelet precursor parameters and said string of wavelet coefficients; a summer for summing said current multiplied precursor parameters with stored prior multiplied precursor function wavelet elements and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving the said intermediate sequence and an output port for outputting an intermediate signal; and (m-1) integrating and buffering stages, each of said integrating and buffering stages comprising an integrator having an input port and an output and a buffer having an input coupled to said output of said integrator and an output port thereof, said input port of a first of said integrating and buffering stages operable to receive said intermediate signal, said mth order wavelet function of said signal appearing at said output port of a last of said integrating and buffering stages in response to said input port of said first stage receiving said intermediate signal.

Claim 18

The wavelet generator of claim 13, wherein each of said integrating and buffering stages comprises: an input port; a resistance for coupling said input port to a first node; a capacitor coupling said first node to ground, a positive input of a first operational amplifier coupled to said node; a second node coupled to a negative input of said first operational amplifier, a third resistance coupling said second node to ground; an output of said first operational amplifier coupled through a third resistance to said second node and through a fourth resistance to said first node; a second operational amplifier having positive and negative inputs and an output, said positive input coupled to said output of said first operational amplifier, said negative input coupled to said output.

Claim 19

A spline generator for generating an mth order spline function of a sequence, comprising: a memory for storing parameters of a B-spline precursor function which, when passed through a digital to analog converter and integrated (m-1) times and buffered (m-1) times, will yield a B-spline of the mth order; a multiplier, a first port of said multiplier receiving said B-spline precursor parameters, a second port of said multiplier receiving a string of spline coefficients derived from said signal, an output of said multiplier outputting a plurality of current multiplied precursor parameters in response to receiving said B-spline precursor parameters and said string of spline coefficients; a summer for summing said current multiplied precursor parameters with stored prior multiplied precursor function spline elements and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving the said intermediate sequence and an output port for outputting an intermediate signal; and (m-1) integrating and buffering stages, each of said integrating and buffering stages comprising an integrator having an input port and an output and a buffer having an input coupled to said output of said integrator and an output port thereof said input port of a first of said integrating and buffering stages operable to receive said intermediate signal, said mth order spline function of said signal appearing at said output port of a last of said integrating and buffering stages in response to said input port of said first stage receiving said intermediate signal.

Claim 20

A spline generator for generating an mth order spline function of a sequence, comprising: a memory for storing parameters of a B-spline precursor function which, when passed through a digital to analog converter and integrated (m-1) times and buffered (m-1) times, will yield a B-spline of the mth order; a multiplier, a first port of said multiplier receiving said B-spline precursor parameters, a second port of said multiplier receiving a string of spline coefficients derived from said signal, an output of said multiplier outputting a plurality of current multiplied precursor parameters in response to receiving said B-spline precursor parameters and said string of spline coefficients; a summer for summing said current multiplied precursor parameters with stored prior multiplied precursor function spline elements and generating an intermediate sequence in response thereto; a digital to analog converter having an input port for receiving the said intermediate sequence and an output port for outputting an intermediate signal; and (m-1) integrating and buffering stages, each of said integrating and buffering stages comprising an integrator having an input port and an output and a buffer having an input coupled to said output of said integrator and an output port thereof said input port of a first of said integrating and buffering stages operable to receive said intermediate signal, said mth order spline function of said signal appearing at said output port of a last of said integrating and buffering stages in response to said input port of said first stage receiving said intermediate signal.

Claim 21

The spline generator of claim 15, wherein each of said integrating and buffering stages comprises: an input port; a resistance for coupling said input port to a first node; a capacitor coupling said first node to ground, a positive input of a first operational amplifier coupled to said node; a second node coupled to a negative input of said first operational amplifier, a third resistance coupling said second node to ground; an output of said first operational amplifier coupled through a third resistance to said second node and through a fourth resistance to said first node; a second operational amplifier having positive and negative inputs and an output, said positive input coupled to said output of said first operational amplifier, said negative input coupled to said output.

Claim 24

The method of claim 17, wherein m is selected to be 2.

Claim 25

The method of claim 17, wherein m is selected to be 4.

Claim 26

The method of claim 17, and further comprising the steps of: processing selected resolution sets of the spline coefficients c k (n) and d k (n) to derive improved signal spline and wavelet coefficients c *k (n) and d *k (n), where k is an integer and varies between zero and q, and q is the order or resolution chosen during decomposition of the signal; reconstructing improved signal spline coefficients c *k+1 (n) according to the formula ##EQU42## where {p j } is a set of spline reconstruction constants and {q j } is a set of wavelet reconstruction constants.

Claim 27

The method of claim 20, and further comprising the steps of reconstructing improved zero-level spline coefficients c *0 (n) by reconstructing the spline coefficients c *k+1 (n), where k varies between the selected order of resolution and zero; and generating a spline F * (t) as an improved approximation of the input analog signal F(t).

Claim 28

A signal analyzer, comprising: a sampler for sampling an input analog signal at a predetermined sampling rate; a digitizer coupled to said sampler for digitizing a plurality of samples resulting from said input analog signal; a B-spline interpolator for generating a plurality of B-spline coefficients of the zero-level in response to receiving the digital signal samples, said interpolator including a multiplier for multiplying a plurality of predetermined stored weights to respective selected ones of the digitized signal samples and a summer for summing the weighted digitized signal samples together in a moving average operation to derive the zero-level B-spline coefficients; and a multiplier for multiplying the zero-level B-spline coefficients in a moving average operation by a plurality of predetermined B n -constants to derive a plurality of first-level wavelet coefficients; a spline function generator for generating at least one spline function from at least one respective set of spline coefficients; and a wavelet generator for generating at least one wavelet function from at least one respective set of wavelet coefficients whereby said input analog signal is processed for analyzing frequency information of said input analog signal.

Claim 29

A signal analyzer, comprising: a sampler for sampling an input analog signal at a predetermined sampling rate; a digitizer coupled to said sampler for digitizing a plurality of samples resulting from said input analog signal; a B-spline interpolator for generating a plurality of B-spline coefficients of the zero-level in response to receiving the digital signal samples, said interpolator including a multiplier for multiplying a plurality of predetermined stored weights to respective selected ones of the digitized signal samples and a summer for summing the weighted digitized signal samples together in a moving average operation to derive the zero-level B-spline coefficients; and a multiplier for multiplying the zero-level B-spline coefficients in a moving average operation by a plurality of predetermined B n -constants to derive a plurality of first-level wavelet coefficients; a spline function generator for generating at least one spline function from at least one respective set of spline coefficients; and a wavelet generator for generating at least one wavelet function from at least one respective set of wavelet coefficients whereby said input analog signal is processed for analyzing frequency information of said input analog signal.

Claim 30

A signal analyzer, comprising: means for receiving a plurality of digital signal samples; means for generating a plurality of spline coefficients of the zero level in response to receiving the digital spline sample, said means for generating including means for multiplying a plurality of predetermined stored weights to respective selected ones of the digitized signal samples and means for summing the weighted digitized signal samples together in a moving average operation to derive zeroth-level B-spline coefficients; means for multiplying the zeroth-level B-spline coefficients in a moving average operation by a plurality of a n -constants to derive a plurality of first-level B-spline coefficients for the signal; means for multiplying the zeroth-level B-spline coefficients in a moving average operation by a plurality of b n -constants to derive a plurality of first-level wavelet coefficients; means for generating at least one spline function from at least one respective set of spline coefficients; and means for generating a wavelet function from at least one respective set of wavelet coefficients whereby said signal is processed for analyzing frequency information of said signal.

Claim 31

A signal analyzer, comprising: means for receiving a plurality of digital signal samples; means for generating a plurality of spline coefficients of the zero level in response to receiving the digital spline sample, said means for generating including means for multiplying a plurality of predetermined stored weights to respective selected ones of the digitized signal samples and means for summing the weighted digitized signal samples together in a moving average operation to derive zeroth-level B-spline coefficients; means for multiplying the zeroth-level B-spline coefficients in a moving average operation by a plurality of a n -constants to derive a plurality of first-level B-spline coefficients for the signal; means for multiplying the zeroth-level B-spline coefficients in a moving average operation by a plurality of b n -constants to derive a plurality of first-level wavelet coefficients; means for generating at least one spline function from at least one respective set of spline coefficients; and means for generating a wavelet function from at least one respective set of wavelet coefficients whereby said signal is processed for analyzing frequency information of said signal.