Vertically stacked bipolar dynamic random access memory

Claim 1

A bipolar DRAM (dynamic random access memory) in which a switching transistor and a storage capacitor are vertically stacked with each other, said DRAM comprising: a semiconductor substrate employed as an emitter region of said transistor; a first impurity layer of a first conductivity type formed on said semiconductor substrate, and being electrically isolated from another impurity layer of said first conductivity type formed on said semiconductor substrate by a field oxide layer therebetween; a base region of a second conductivity type formed on said first impurity layer and forming a first laminate structure with said first impurity layer; a second impurity layer of said first conductivity type formed on said base region; a collector region formed on said second impurity layer thereby forming a second laminate structure with said second impurity layer; first and second spacers, respectively formed along side-walls of said laminate structure of said second impurity layer and said collector region; first and second word lines respectively formed along sidewalls of a third laminate structure comprised of said base region and said first and second spacers; a first storage node of said capacitor formed on said collector region, electrically isolated with a second storage node by an insulating layer therebetween; a dielectric layer formed on a surface of said first storage node; and a plate electrode formed on said dielectric layer and said insulating layer.