Abstract Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate. In the fabrication of the heterojunction bipolar transistor circuits, the P-ohmic contacts on both the NPN and PNP materials is evaporated at the appropriate locations simultaneously. All of the N-ohmic contacts are also deposited simultaneously. By this, the complementary dual heterojunction bipolar transistor device can be effectively fabricated with excellent DC and microwave capabilities.
A method of producing a desirable configuration of transistor devices on a common substrate, said method comprising the steps of: fabricating NPN and PNP profiles adjacent to each other on the substrate, the NPN and PNP profiles each including at least an emitter region, a base region, and a collector region; developing emitter mesas and base mesas on each NPN and PNP profile; simultaneously evaporating P-ohmic contacts on the base regions of the NPN profiles and the emitter and collector regions of the PNP profiles; annealing the P-ohmic contacts; simultaneously evaporating N-ohmic contacts on the emitter and collector regions of the NPN profiles and base regions of the PNP profile; and annealing the N-ohmic contacts.
Claim 2
Independent Claim
115 words
A method of producing a desirable configuration of transistor devices on a common substrate, said method comprising the steps of: fabricating NPN and PNP profiles adjacent to each other on the substrate, the NPN and PNP profiles each including at least an emitter region, a base region, and a collector region; developing emitter mesas and base mesas on each NPN and PNP profile; simultaneously evaporating P-ohmic contacts on the base regions of the NPN profiles and the emitter and collector regions of the PNP profiles; annealing the P-ohmic contacts; simultaneously evaporating N-ohmic contacts on the emitter and collector regions of the NPN profiles and base regions of the PNP profile; and annealing the N-ohmic contacts.
Claim 3
Dependent Claim
30 words
The method according to claim 1 wherein the method of producing a desirable configuration of transistor devices is a method of producing a desirable configuration of heterojunction bipolar transistor devices.
Claim 4
Dependent Claim
31 words
The method according to claim 1 wherein the step of fabricating NPN and PNP profiles includes the step of fabricating the NPN and PNP profiles by means of molecular beam epitaxy.
Claim 5
Dependent Claim
25 words
The method according to claim 1 wherein the steps evaporating P-ohmic contacts and N-ohmic contacts includes evaporating gold-beryllium contacts by means of electron beam evaporation.
Claim 6
Dependent Claim
33 words
The method according to claim 1 further comprising the step of depositing a dielectric layer after the step of evaporating the P-ohmic contacts, but prior to the step of annealing the P-ohmic contacts.
Claim 7
Dependent Claim
34 words
The method according to claim 1 further comprising the steps of depositing subsequent layers including dielectric layers, a thin film resistance layer and associated contact layers to provide the desirable configuration of transistor devices.