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Process of manufacturing semiconductor devices

Assignee: Renesas Electronics Corp
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Filing: 1991-06-12
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Granted: 1993-11-16
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Expires: 2011-06-12
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Abstract

Abstract A process of manufacturing semiconductor devices includes a step of transferring on a surface of a semiconductor wafer by a step-and-repeat reduction projection system a pair of rotation error check patterns formed as a main scale and a vernier scale. In one form, the transfer also includes a pair of resolution check patterns disposed respectively adjacent to the main scale and the vernier scale. In another form, the process includes a first step of transferring a mask pattern including a main or a vernier alignment scale having an alignment check patterns and a second step of transferring, after the completion of said first step, another mask pattern including another main or vernier alignment scale having an alignment check patterns and this second step includes transferring of rotation error check patterns and resolution check patterns. The process includes a step of observing such patterns which enables to detect any rotation errors, resolution deficiency or alignment errors through microscopic fields of vision.

Inventors

  • 👤 Masayuki Yanagisawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 12:51
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70633; H10W; H10W46/00; H10W46/301

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 175 words
A process of manufacturing semiconductor devices including: a step of transferring on a surface of a semiconductor wafer by a step-and-repeat reduction projection system a pair of rotation error check patterns and a pair of resolution check patterns, said rotation error check patterns being formed as a pair of scales, one being a main scale disposed in a first scribe line region adjacent to and in parallel with a first side of a circuit region and the other being a vernier scale disposed in a second scribe line region adjacent to and in parallel with a second side of said circuit region opposite to said first side, and said resolution check patterns being formed as a first resolution check pattern and a second resolution check pattern disposed respectively adjacent to said main scale and said vernier scale; and a step of simultaneously observing said rotation error check patterns and said resolution check patterns in a single field of vision of a microscope for detecting any rotation errors and any resolution deficiency on a resist film.
Claim 2
Dependent Claim 175 words
A process of manufacturing semiconductor devices including: a step of transferring on a surface of a semiconductor wafer by a step-and-repeat reduction projection system a pair of rotation error check patterns and a pair of resolution check patterns, said rotation error check patterns being formed as a pair of scales, one being a main scale disposed in a first scribe line region adjacent to and in parallel with a first side of a circuit region and the other being a vernier scale disposed in a second scribe line region adjacent to and in parallel with a second side of said circuit region opposite to said first side, and said resolution check patterns being formed as a first resolution check pattern and a second resolution check pattern disposed respectively adjacent to said main scale and said vernier scale; and a step of simultaneously observing said rotation error check patterns and said resolution check patterns in a single field of vision of a microscope for detecting any rotation errors and any resolution deficiency on a resist film.

References Cited (Backward Citations)

US4388386A Cited
US4642672A Cited
US4610940A Cited
JPS62115165A Cited
US4806457A Cited
JPH01193743A Cited
EP0370834A2 Cited
US5017514A Cited
JPH0358408A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-11-15 1997-05-17 1997-11-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-11-15 2001-05-17 2001-11-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-11-15 2005-05-17 2005-11-16 $7700.00 Window Closed / Lapsed

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