Patent US5261116A successfully refreshed from Google Patents.
US5261116A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable, expandable controller with flexible I/O
Assignee: Lattice Semiconductor Corp
•
Filing: 1992-06-01
•
Granted: 1993-11-09
•
Expires: 2012-06-01
Abstract
Abstract A programmable controller which combines microaddress control logic, memory, a microinstruction decoder, and I/O into a unitary, integrated device. The microaddress control logic is responsive to sequencing signals developed by the microinstruction decoder, and includes an address generator which develops the program address. The memory, which can be either PROM or RAM, is addressed by the address and outputs a microinstruction word to a pipeline register. The microinstruction word has an internal field which is coupled to inputs of the microaddress control logic and the microinstruction decoder, and a control field which is coupled to an output buffer. The output buffer includes multiplexers which permit either the program count or the control field to be multiplexed to the output pins of the device. When the program address is multiplexed to the output pins, the programmable controller can address external memory devices.
Inventors
- 👤 Om P. Agrawal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223; G06F9/26; G06F9/262; G06F9/264
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
164 words
In a programmable controller including microaddress control logic, a memory, and microinstruction decoder logic; an improved microaddress control logic circuit comprising: a branch control logic responsive to at least a portion of an internal field of a microinstruction word, said branch control logic being operative to develop branch control signals; a loop counter coupled to said branch control logic and responsive to a number of said branch control signals, said loop counter being operative to develop a loop count signal; a program counter coupled to said branch control logic and responsive to a number of said branch control signals, said program counter being operative to develop a program count signal; and stack means coupled to said loop counter and said program counter for selectively storing outputs thereof, said stack means being operative to develop a stack output signal, wherein said stack means includes a stack multiplexer, a stack pointer coupled to outputs of said stack multiplexer, and stack memory addressed by said stack pointer.
Claim 2
Dependent Claim
164 words
In a programmable controller including microaddress control logic, a memory, and microinstruction decoder logic; an improved microaddress control logic circuit comprising: a branch control logic responsive to at least a portion of an internal field of a microinstruction word, said branch control logic being operative to develop branch control signals; a loop counter coupled to said branch control logic and responsive to a number of said branch control signals, said loop counter being operative to develop a loop count signal; a program counter coupled to said branch control logic and responsive to a number of said branch control signals, said program counter being operative to develop a program count signal; and stack means coupled to said loop counter and said program counter for selectively storing outputs thereof, said stack means being operative to develop a stack output signal, wherein said stack means includes a stack multiplexer, a stack pointer coupled to outputs of said stack multiplexer, and stack memory addressed by said stack pointer.
Claim 3
Dependent Claim
49 words
A microaddress control logic circuit as recited in claim 1 wherein said loop counter includes a counter multiplexer having inputs coupled to a number of said branch control signals; and a counter register coupled to outputs of said loop counter multiplexer, said counter register developing said loop count signal.
Claim 4
Dependent Claim
47 words
A microaddress control logic circuit as recited in claim 2 wherein said loop counter further includes a decrementer coupled to said counter register for developing a decremented count signal from said loop count signal, where said decremented count signal is coupled to inputs of said counter multiplexer.
Claim 5
Dependent Claim
30 words
A microaddress control logic circuit as recited in claim 2 further comprising a zero detector responsive to said loop count signal and operative to develop a zero detection signal therefrom.
Claim 6
Dependent Claim
21 words
A microaddress control logic circuit as recited in claim 2 wherein said counter multiplexer has inputs coupled to said stack means.
Claim 7
Dependent Claim
60 words
A microaddress control logic circuit as recited in claim 1 wherein said program counter includes a program counter multiplexer, a program counter register coupled to outputs of said program counter multiplexer for developing said program count signal, and an incrementer coupled to said program counter register and operative to develop an incremented program counter signal from said program counter signal.
Claim 8
Dependent Claim
33 words
A microaddress control logic circuit as recited in claim 6 wherein said program counter multiplexer has inputs coupled to said branch control logic, said stack means, said program counter register, and said incrementer.
Claim 9
Dependent Claim
34 words
A microaddress control logic circuit as recited in claim 1, wherein said stack means is further coupled to said branch control logic and is responsive to at least one of said branch control signals.
Claim 10
Dependent Claim
30 words
A microaddress control logic circuit as recited in claim 1 wherein said stack multiplexer has inputs coupled to said branch control logic, said program counter, and to said loop counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |