Apparatus evaluating the data rates of virtual circuits occupying an asynchronous time-multiplexed transmission path

Claim 1

An apparatus for evaluating a data rate of virtual circuits conveying cells and occupying an asynchronous time-multiplexed transmission path, the apparatus comprising: a memory in which each virtual circuit is allocated space containing "context" data, defining data rate evaluation conditions of the virtual circuit and containing information resulting from earlier stages in evaluation, a clock organized to deliver a current time, processor means coupled to said memory and said clock for reading a context of a given virtual circuit to which a given cell belongs upon reception of said given cell, said context containing a starting time which was the current time as observed and recorded when an earlier cell of said given virtual circuit was received, said processor means subtracting said starting time from a present current time to establish a time difference, and said processor means evaluating said data rate in accordance with the time difference together with a number of cells observed between said given cell and the earlier cell, wherein the apparatus further includes means for cyclically scanning said context and, during said cyclic scanning, incrementing a scan cycle counter in each context, which counter has an initial position, together with additional means responsive to the arrival of a cell for reading the scan cycle counter, determining the position of said scan cycle counter relative to its initial position, and when said relative position corresponds to a given number of scan cycles, said given number being greater than one, inhibiting any repressive countermeasures.

Claim 2

An apparatus for evaluating a data rate of virtual circuits conveying cells and occupying an asynchronous time-multiplexed transmission path, the apparatus comprising: a memory in which each virtual circuit is allocated space containing "context" data, defining data rate evaluation conditions of the virtual circuit and containing information resulting from earlier stages in evaluation, a clock organized to deliver a current time, processor means coupled to said memory and said clock for reading a context of a given virtual circuit to which a given cell belongs upon reception of said given cell, said context containing a starting time which was the current time as observed and recorded when an earlier cell of said given virtual circuit was received, said processor means subtracting said starting time from a present current time to establish a time difference, and said processor means evaluating said data rate in accordance with the time difference together with a number of cells observed between said given cell and the earlier cell, wherein the apparatus further includes means for cyclically scanning said context and, during said cyclic scanning, incrementing a scan cycle counter in each context, which counter has an initial position, together with additional means responsive to the arrival of a cell for reading the scan cycle counter, determining the position of said scan cycle counter relative to its initial position, and when said relative position corresponds to a given number of scan cycles, said given number being greater than one, inhibiting any repressive countermeasures.