Multiport memory device

Claim 2

A multiport memory device comprising: a power source; a memory cell for storing data; a first bit line; a first word line; a first switch which has an input section connected to said first word line and a current path whose one end is connected to said first bit line, and which provides on/off control according to the potential of said first word line; a second bit line; a second word line; a second switch which has an input section connected to said second word line and a current path whose one end is connected to said second bit line, and which provides on/off control according to the potential of said second word line; and a third switch which has an input section connected to said memory cell and a current path whose one end is connected to both the other end of the current path of said first switch and the other end of the current path of said second switch and whose other end is connected to said power source, and which provides on/off control according to the presence/absence of data in said memory cell.

Claim 3

A multiport memory device according to claim 1, wherein said memory cell is a latch circuit constructed in such a manner that the output of a first inverter is connected to the input of a second inverter and the output of said second inverter is connected to the input of said first inverter, with the input section of said third switch being connected to the junction of the output of said first inverter and the input of said second inverter.

Claim 4

A multiport memory device according to claim 2, wherein said first switch, said second switch, and said third switch are each made up of insulated-gate FETs.

Claim 5

A multiport memory device according to claim 1, further comprising: a third bit line; a third word line; a fourth switch which has an input section connected to said third word line and a current path whose one end is connected to said memory cell and whose other end is connected to said third bit line, and which provides on/off control according to the potential of said third word line.

Claim 6

A multiport memory device according to claim 4, wherein: said first word line and said second word line, when reading the data from said memory cell, are each placed at a potential that turns on at least one of said first switch and said second switch; and said third word line, when writing the data in said memory cell, is placed at a potential that turns on at least said fourth switch.

Claim 7

A multiport memory device according to claim 5, wherein said memory cell is a latch circuit constructed in such a manner that the output of a first inverter is connected to the input of a second inverter and the output of said second inverter is connected to the input of said first inverter, with the input section of said third switch being connected to the junction of the output of said first inverter and the input of said second inverter, and one end of the current path of said fourth switch being connected to the junction of the output of said second inverter and the input of said first inverter.

Claim 8

A multiport memory device according to claim 6, wherein said first switch, said second switch, said third switch, and said fourth switch are each made up of insulated-gate FETs.

Claim 9

A multiport memory device according to claim 4, further comprising: a fourth bit line; a fourth word line; a fifth switch which has an input section connected to said fourth word line and a current path whose one end is connected to one end of the current path of said fourth switch, and whose other end is connected to said fourth bit line, and which provides on/off control according to the potential of said third word line.

Claim 10

A multiport memory device according to claim 8, wherein: said first word line and said second word line, when reading the data from said memory cell, are each placed at a potential that turns on at least one of said first switch and said second switch; and said third word line and said fourth word line, when writing the data in said memory cell, are each placed at a potential that turns on at least one of said fourth switch and said fifth switch.

Claim 11

A multiport memory device according to claim 9, wherein said memory cell is a latch circuit constructed in such a manner that the output of a first inverter is connected to the input of a second inverter and the output of said second inverter is connected to the input of said first inverter, with the input section of said third switch being connected to the junction of the output of said first inverter and the input of said second inverter, and one end of the current path of each of said fourth switch and said fifth switch being connected to the junction of the output of said second inverter and the input of said first inverter.

Claim 12

A multiport memory device according to claim 10, wherein said first switch, said second switch, said third switch, said fourth switch, and said fifth switch are each made up of insulated-gate FETs.

Claim 13

A multiport memory device comprising: a power source; a latch circuit constructed in such a manner that the output of a first inverter is connected to the input of a second inverter and the output of said second inverter is connected to the input of said first inverter; a first bit line; a first word line; a first switch which has an input section connected to said first word line and a current path whose one end is connected to said first bit line, and which provides on/off control according to the potential of said first word line; a second bit line; a second word line; a second switch which has an input section connected to said second word line and a current path whose one end is connected to said second bit line, and which provides on/off control according to the potential of said second word line; and a third switch which has an input section connected to a first junction of the output of said first inverter and the input of said second inverter and a current path whose one end is connected to both the other end of the current path of said first switch and the other end of the current path of said second switch and whose other end is connected to said power source, and which provides on/off control according to the potential of said first junction; a third bit line; a third word line; a fourth switch which has an input section connected to said third word line and a current path whose one end is connected to said third bit line, and which provides on/off control according to the potential of said third word line. a fourth bit line; a fourth word line; a fifth switch which has an input section connected to said fourth word line and a current path whose one end is connected to said fourth bit line, and which provides on/off control according to the potential of said fourth word line; and a sixth switch which has an input section connected to a second junction of the output of said second inverter and the input of said first inverter and a current path whose one end is connected to both the other end of the current path of said fourth switch and the other end of the current path of said fifth switch and whose other end is connected to said power source, and which provides on/off control according to the potential of said second junction.

Claim 14

A multiport memory device comprising: a power source; a latch circuit constructed in such a manner that the output of a first inverter is connected to the input of a second inverter and the output of said second inverter is connected to the input of said first inverter; a first bit line; a first word line; a first switch which has an input section connected to said first word line and a current path whose one end is connected to said first bit line, and which provides on/off control according to the potential of said first word line; a second bit line; a second word line; a second switch which has an input section connected to said second word line and a current path whose one end is connected to said second bit line, and which provides on/off control according to the potential of said second word line; and a third switch which has an input section connected to a first junction of the output of said first inverter and the input of said second inverter and a current path whose one end is connected to both the other end of the current path of said first switch and the other end of the current path of said second switch and whose other end is connected to said power source, and which provides on/off control according to the potential of said first junction; a third bit line; a third word line; a fourth switch which has an input section connected to said third word line and a current path whose one end is connected to said third bit line, and which provides on/off control according to the potential of said third word line. a fourth bit line; a fourth word line; a fifth switch which has an input section connected to said fourth word line and a current path whose one end is connected to said fourth bit line, and which provides on/off control according to the potential of said fourth word line; and a sixth switch which has an input section connected to a second junction of the output of said second inverter and the input of said first inverter and a current path whose one end is connected to both the other end of the current path of said fourth switch and the other end of the current path of said fifth switch and whose other end is connected to said power source, and which provides on/off control according to the potential of said second junction.

Claim 15

A multiport memory device according to claim 12, wherein said first switch, said second switch, said third switch, said fourth switch, said fifth switch, and said sixth switch are each made up of insulated-gate FETs.

Claim 16

A multiport memory device according to claim 12, further comprising: a fifth bit line; a fifth word line; a seventh switch which has an input section connected to said fifth word line and a current path whose one end is connected to a first junction of the output of said first inverter and the input of said second inverter and whose other end is connected to said fifth bit line, and which provides on/off control according to the potential of said fifth word line; a sixth bit line; a fifth word line; an eighth switch which has an input section connected to said sixth word line and a current path whose one end is connected to a second junction of the output of said second inverter and the input of said first inverter and whose other end is connected to said sixth bit line, and which provides on/off control according to the potential of said sixth word line.

Claim 17

A multiport memory device according to claim 14, wherein: said first word line, said second word line, said third word line, and said fourth word line, when reading the data from said latch circuit, are each placed at a potential that turns on at least one of said first switch, said second switch, said third switch, and said fourth switch; and said fifth word line and said sixth word line, when writing the data in said latch circuit, are each placed at a potential that turns on at least one of said seventh switch and said eighth switch.

Claim 18

A multiport memory device according to claim 15, wherein said first switch, said second switch, said third switch, said fourth switch, said fifth switch, said sixth switch, said seventh switch, and said eighth switch are each made up of insulated-gate FETs.

Claim 19

A multiport memory device according to claim 14, further comprising: a seventh bit line; a seventh word line; a ninth switch which has an input section connected to said seventh word line and a current path whose one end is connected to said first junction and whose other end is connected to said seventh bit line, and which provides on/off control according to the potential of said seventh word line; an eighth bit line; an eighth word line; and a tenth switch which has an input section connected to said eighth word line and a current path whose one end is connected to said second junction and whose other end is connected to said eighth bit line, and which provides on/off control according to the potential of said eighth word line.

Claim 20

A multiport memory device according to claim 17, wherein: said first word line, said second word line, said third word line, and said fourth word line, when reading the data from said latch circuit, are each placed at a potential that turns on at least one of said first switch, said second switch, said third switch, and said fourth switch; and said fifth word line, said sixth word line, said seventh word line, and said eighth word line, when writing the data in said latch circuit, are each placed at a potential that turns on at least one of said seventh switch, said eighth switch, said ninth switch, and said tenth switch.

Claim 21

A multiport memory device according to claim 18, wherein said first switch, said second switch, said third switch, said fourth switch, said fifth switch, said sixth switch, said seventh switch, said eighth switch, said ninth switch, and said tenth switch are each made up of insulated-gate FETs.