Patent US5260905A successfully refreshed from Google Patents.
US5260905A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-port memory
Assignee: Panasonic Holdings Corp
•
Filing: 1991-09-03
•
Granted: 1993-11-09
•
Expires: 2011-09-03
Abstract
Abstract The multi-port memory of the present invention is provided with a random port for describing the graphic data, a first serial port for reading the data to be displayed, and a second serial port for writing the dynamic picture image data and which has a transfer mask register to transfer the dynamic picture image to a window. The multi-port memory enables multi-window display of the dynamic picture images in a simple circuit structure, with ensuring high-speed erasure and scroll of the multi-window.
Inventors
- 👤 Toshiki Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
143 words
A multi-port memory which is a semiconductor memory device comprising: a memory array comprising means for a random access function; a first serial access memory comprising a first data register for retrieving data stored in the memory array serially in synchronization with a first clock; a second serial access memory comprising a second data register for storing input data serially in synchronization with a second clock, transfer mask data input means for inputting transfer mask data to control the transfer of serial data to the memory array and a third data register for storing the transfer mask data from the transfer mask data input means in synchronization with the second clock; and control means for controlling the transfer of each bit of serial data from the second serial access memory to the memory array in accordance with outputs from the third data register.
Claim 2
Dependent Claim
143 words
A multi-port memory which is a semiconductor memory device comprising: a memory array comprising means for a random access function; a first serial access memory comprising a first data register for retrieving data stored in the memory array serially in synchronization with a first clock; a second serial access memory comprising a second data register for storing input data serially in synchronization with a second clock, transfer mask data input means for inputting transfer mask data to control the transfer of serial data to the memory array and a third data register for storing the transfer mask data from the transfer mask data input means in synchronization with the second clock; and control means for controlling the transfer of each bit of serial data from the second serial access memory to the memory array in accordance with outputs from the third data register.
Claim 3
Dependent Claim
40 words
The multi-port memory of claim 1 wherein the second serial access memory further comprises: a selector means which selects either the transfer mask data from the transfer mask data input means or the transfer mask data generated inside the memory.
Claim 4
Dependent Claim
121 words
The multi-port memory of claim 1 wherein the second serial access memory further comprises: address signal input means for designating a starting bit position where said second and third registers start to load the said input data and said transfer mask data, respectively; a serial address counter which counts the number of clock cycles after loading an address signal from said address signal input means so as to generate a serial address moving sequentially upward form said starting bit position to a more significant bit position; and a serial bit selector which selects the bit position designated by said serial address counter; whereby only the data of the desired bits stored in the second register are transferred to the memory array.
Claim 5
Dependent Claim
56 words
The multi-port memory of claim 1 wherein the first serial access memory comprises: a serial data output port; a serial data register for storing data transferred from the memory array; and means for transferring an arbitrary number of data bits stored in the serial data register to the serial data output port in a sequential manner.
Claim 6
Dependent Claim
23 words
The multi-port memory of claim 1 wherein the memory array comprises a random port for reading and writing data in the memory array.
References Cited (Backward Citations)
JPH02158996A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |