Patent US5260861A successfully refreshed from Google Patents.
US5260861A
Expired / Lapsed
US
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Digital controlled converter and method
Assignee: BR0DEUR-WERT LLC
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Filing: 1992-05-01
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Granted: 1993-11-09
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Expires: 2012-05-01
Abstract
Abstract A digital controlled converter (100) for converting an input signal to a direct current signal having a clock generator (104) for generating a high frequency clock timing signal and a driver circuit (106) for controlling the passage of the high frequency clock timing signal within the converter (100). A power output stage (102) which provides an output signal is controlled by the driver circuit (106). A control loop (108) is provided for sensing and converting the output signal to a command signal. A latch (128) is utilized for latching the command signal and for controlling the state of the driver circuit (106). The latch (128) is reset at the rate of the high frequency clock timing signal and updated with the command signal to provide incremental correction to the output signal. The converter (100) comprises a transient response to variations in load proportional to the high frequency clock timing signal. In a preferred embodiment, the driver circuit (106) functions as a switch for controlling the power output stage (102). The control loop ( 108) serves to provide the command signal to operate the latch (128). A comparator (138) in the control loop compares the d.c. output signal with an analog reference signal to generate the command signal. In an alternative embodiment, the d.c. output signal is converted to a digital signal and compared to a reference digital word in a digital comparator (292) to provide the command signal.
Inventors
- 👤 Harry E. Wert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:48
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/33507; H02M3/33515; H02M3/337; H02M3/3376; H02M3/3378
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
125 words
A digital controlled converter comprising: means for generating a high frequency clock timing signal; switching means for controlling the passage of said high frequency clock timing signal within said converter; power means for providing an output signal, said power means controlled by said switching means; control loop means for sensing and converting said output signal to a command signal; and means for latching said command signal and for controlling the state of said switching means, said latching and controlling means being reset at the rate of said high frequency clock timing signal and updated with said command signal to provide incremental correction to said output signal wherein said converter comprises a transient response to variations in load proportional to said high frequency clock timing signal.
Claim 2
Dependent Claim
125 words
A digital controlled converter comprising: means for generating a high frequency clock timing signal; switching means for controlling the passage of said high frequency clock timing signal within said converter; power means for providing an output signal, said power means controlled by said switching means; control loop means for sensing and converting said output signal to a command signal; and means for latching said command signal and for controlling the state of said switching means, said latching and controlling means being reset at the rate of said high frequency clock timing signal and updated with said command signal to provide incremental correction to said output signal wherein said converter comprises a transient response to variations in load proportional to said high frequency clock timing signal.
Claim 3
Dependent Claim
16 words
The digital controlled converter of claim 1 wherein said generating means includes a clock pulse generator.
Claim 4
Dependent Claim
16 words
The digital controlled converter of claim 1 wherein said switching means includes an electronic driver circuit.
Claim 5
Dependent Claim
17 words
The digital controlled converter of claim 1 wherein said power means includes an electronic power output stage.
Claim 6
Dependent Claim
31 words
The digital controlled converter of claim 1 wherein said control loop means includes a loop sense point and a comparator to sense and convert said output signal to said command signal.
Claim 7
Dependent Claim
21 words
The digital controlled converter of claim 1 wherein said control loop means includes a resistor ladder for providing a reference voltage.
Claim 8
Dependent Claim
23 words
The digital controlled converter of claim 1 wherein said control loop means includes a voltage select device for providing a digital word reference.
Claim 9
Dependent Claim
26 words
The digital controlled converter of claim 1 wherein said control loop means includes an analog-to-digital converter for converting said output signal to an equivalent digital signal.
Claim 10
Dependent Claim
16 words
The digital controlled converter of claim 1 wherein said latching and controlling means comprises a latch.
Claim 11
Dependent Claim
23 words
The digital controlled converter of claim 1 further including a cross-conduction circuit to prevent simultaneous operation of multiple stages in said power means.
Claim 12
Dependent Claim
21 words
The digital controlled converter of claim 1 further including a transformer magnetic for isolating said power means from an output terminal.
Claim 13
Dependent Claim
22 words
The digital controlled converter of claim 1 further including a rectifier circuit for converting said output signal to a direct current signal.
Claim 14
Dependent Claim
19 words
The digital controlled converter of claim 1 further including an over-voltage circuit for sensing and terminating an over-voltage condition.
Claim 15
Dependent Claim
19 words
The digital controlled converter of claim 1 further including an over-current circuit for sensing and terminating an over-current condition.
Claim 16
Dependent Claim
129 words
A digital controlled converter comprising: a clock generator for generating a high frequency clock timing signal; a driver circuit for controlling the passage of said high frequency clock timing signal within said converter; a power output stage for providing an output signal, said power output stage controlled by said driver circuit; control loop means for sensing and converting said output signal to a command signal; and a latch for latching said command signal and for controlling the state of said driver circuit, said latch being reset at the rate of said high frequency clock timing signal and updated with said command signal to provide incremental correction to said output signal wherein said converter comprises a transient response to variations in load proportional to said high frequency clock timing signal.
Claim 17
Dependent Claim
129 words
A digital controlled converter comprising: a clock generator for generating a high frequency clock timing signal; a driver circuit for controlling the passage of said high frequency clock timing signal within said converter; a power output stage for providing an output signal, said power output stage controlled by said driver circuit; control loop means for sensing and converting said output signal to a command signal; and a latch for latching said command signal and for controlling the state of said driver circuit, said latch being reset at the rate of said high frequency clock timing signal and updated with said command signal to provide incremental correction to said output signal wherein said converter comprises a transient response to variations in load proportional to said high frequency clock timing signal.
Claim 18
Independent Claim
126 words
A method for providing digital controlled conversion of an input signal to a direct current signal, said method comprising the steps of: generating a high frequency clock timing signal; controlling the passage of said high frequency clock timing signal with a driver circuit; providing an output signal from an output stage controlled by said driver circuit; sensing and converting said output signal to a command signal; latching said command signal and controlling the state of said driver circuit with a latch; resetting said latch at the rate of said high frequency clock timing signal; updating said latch with said command signal to provide incremental correction to said output signal; and providing a transient response to variations in load proportional to said high frequency clock timing signal.
Claim 19
Independent Claim
126 words
A method for providing digital controlled conversion of an input signal to a direct current signal, said method comprising the steps of: generating a high frequency clock timing signal; controlling the passage of said high frequency clock timing signal with a driver circuit; providing an output signal from an output stage controlled by said driver circuit; sensing and converting said output signal to a command signal; latching said command signal and controlling the state of said driver circuit with a latch; resetting said latch at the rate of said high frequency clock timing signal; updating said latch with said command signal to provide incremental correction to said output signal; and providing a transient response to variations in load proportional to said high frequency clock timing signal.
Claim 20
Dependent Claim
22 words
The method of claim 16 further including the step of isolating said output stage from an output terminal with a transformer magnetic.
Claim 21
Dependent Claim
23 words
The method of claim 16 further including the step of converting said output signal to a direct current signal in a rectifier circuit.
Claim 22
Dependent Claim
20 words
The method of claim 16 further including the step of sensing and terminating an over-voltage condition with an over-voltage circuit.
Claim 23
Dependent Claim
20 words
The method of claim 16 further including the step of sensing and terminating an over-current condition with an over-current circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |