Patent US5260839A successfully refreshed from Google Patents.
US5260839A
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Time base corrector
Assignee: Panasonic Holdings Corp
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Filing: 1991-03-18
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Granted: 1993-11-09
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Expires: 2011-03-18
Abstract
Abstract An input video signal is converted into a digital signal by a clock of a predetermined time interval. Of the time base errors included in the above signal, time base errors of the clock unit are corrected by resetting the write address of the memory, and time base errors of less than the clock unit and velocity errors are corrected by an interpolation filter provided at a later stage of the memory. By the above processing, it is possible to correct time base errors by only a clock of a predetermined interval and it is also possible to improve interface characteristics with other digital processing sections.
Inventors
- 👤 Toyohiko Matsuta
- 👤 Tokikazu Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:24
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/896
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
209 words
A time base corrector comprising: a clock generator for generating a clock signal of a constant time interval; an A/D converter for sampling an input signal by a clock signal produced from said clock generator and for converting the sampled signal into a digital signal; a memory for temporarily storing a digital signal obtained by said A/D converter; a horizontal synchronizing detector for detecting a horizontal synchronizing signal in said digital signal obtained by said A/D converter and for outputting a detected horizontal synchronizing signal; a write address generator for resetting a write address of said memory each time when said detected horizontal synchronizing signal is detected; a time base error detector for detecting a time base error in the digital signal obtained by said A/D converter and for outputting time base error information to be used for an interpolation based on the detected error; an interpolation filter for obtaining a digital signal having a reference time base by interpolating an amplitude of a digital signal produced from said memory based on time base error information produced from said time base error detector; and a D/A converter for converting an output signal from said interpolation filter into an analog signal by a clock signal produced from said clock generator.
Claim 2
Dependent Claim
209 words
A time base corrector comprising: a clock generator for generating a clock signal of a constant time interval; an A/D converter for sampling an input signal by a clock signal produced from said clock generator and for converting the sampled signal into a digital signal; a memory for temporarily storing a digital signal obtained by said A/D converter; a horizontal synchronizing detector for detecting a horizontal synchronizing signal in said digital signal obtained by said A/D converter and for outputting a detected horizontal synchronizing signal; a write address generator for resetting a write address of said memory each time when said detected horizontal synchronizing signal is detected; a time base error detector for detecting a time base error in the digital signal obtained by said A/D converter and for outputting time base error information to be used for an interpolation based on the detected error; an interpolation filter for obtaining a digital signal having a reference time base by interpolating an amplitude of a digital signal produced from said memory based on time base error information produced from said time base error detector; and a D/A converter for converting an output signal from said interpolation filter into an analog signal by a clock signal produced from said clock generator.
Claim 3
Dependent Claim
117 words
A time base corrector according to claim 1, wherein said interpolation filter comprises: delay means having cascade connection of a plurality of delay circuits for obtaining a plurality of sample values by delaying an input signal of said interpolation means; selectors for selecting a predetermined number of sample values from said plurality of delay circuits based on time base error information from the time base error detector; a plurality of multipliers for multiplying a predetermined number of sample values selected by said selectors with coefficients based on time base error information from said time base error detector; and an adder for adding outputs from said plurality of multipliers to obtain an interpolation output from said interpolation filter.
Claim 4
Dependent Claim
76 words
A time base corrector according to claim 1, wherein said time base error detector has a time base error calculating circuit for obtaining and outputting a time base error smaller than one clock time of said clock signal in a digital signal by an arithmetic operation, and outputs time base errors to be corrected for each time when said detected horizontal synchronizing signal is received by using an output from said time base error calculating circuit.
Claim 5
Dependent Claim
110 words
A time base corrector according to claim 1, wherein said time base error detector comprises: a time base error calculating circuit for obtaining and outputting a time base error smaller than one clock time of said clock signal in a digital signal by an arithmetic operation; and a velocity error detector for obtaining an error from a fixed predetermined reference horizontal scanning time by using an output from said time base error calculating circuit; and produces output time base errors to be corrected for each clock time of said clock signal by using an output from said time base error calculating circuit and an output from said velocity error detector.
References Cited (Backward Citations)
US3931638A
Cited
US4120000A
Cited
EP0217091A1
Cited
US4802026A
Cited
US4882633A
Cited
EP0300633A2
Cited
US4905101A
Cited
US5072315A
Cited
US4975788A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |