Analog-to-digital converter having selectively and independently controllable sampling and conversion periods

Claim 2

An analog-to-digital converter comprising: a sampling circuit for sampling analog signal during a sampling period; a conversion circuit, operatively connected to said sampling circuit, for converting the analog signal sampled by said sampling circuit to a digital signal during a conversion period; and a control circuit, operatively connected to said sampling circuit and said converting circuit, for independently controlling the respective durations of the sampling period and the conversion period.

Claim 3

An analog-to digital converter according to claim 1, wherein said control circuit controls the respective durations of the sampling period and the conversion period in accordance with control information.

Claim 4

An analog-to-digital converter according to claim 2, wherein: said sampling circuit operates in accordance with a first clock signal; and said conversion circuit operates in accordance with a second clock signal; said control circuit comprises a clock supply circuit for supplying the first and second clock signals, the clock supply circuit independently varying the respective frequencies of the first and second clock signals in accordance with said control information.

Claim 5

An analog-to-digital converter according to claim 3, wherein said clock supply circuit comprises a clock generating circuit for providing a plurality of clock signals having respective, different frequencies and a switch circuit for selecting the first and second clock signals from the plurality of clock signal sin accordance with said control information.

Claim 6

An analog-to-digital converter according to claim 4, wherein said clock supply circuit further comprises a control register means, operatively connected to the switch circuit, for storing the control information.

Claim 7

An analog-to-digital converter according to claim 4, wherein the clock generating circuit comprises at least one of a frequency divider circuit and a frequency multiplying circuit, each thereof having a plurality of outputs.

Claim 8

An analog-to-digital converter according to claim 1, wherein said analog-to-digital converter is formed in semiconductor substrate, said sampling circuit operates in accordance with a first clock signal, said conversions circuit operates in accordance with a second clock signal, and wherein said control circuit comprises a clock generating circuit for providing plurality of clock signals having respective, different frequencies and a wiring pattern which affords independent selection of the respective frequencies of the first and second clock signals from the plurality of clock signals by a master-slice method.

Claim 9

An analog-to-digital converter according to claim 3, further comprising: a microcomputer, said analog-to-digital converter and said microcomputer thereof being commonly formed in a semiconductor substrate; said control circuit further comprising control register means for storing the control information and a data bus; and said microcomputer comprising a data processing unit connected to the control register means via the data bus, the sampling period and the conversion period being individually programmable under control of the data processing unit.

Claim 10

An analog-to-digital converter according to claim 1, wherein: said conversion circuit comprises: a comparator for comparing the analog signal with a reference analog signal, a sequential comparison controller, operatively connected to the comparator, for providing and varying the digital signal in accordance with an output of the comparator, and a digital-to-analog converter for converting the digital signal to the reference analog signal; and said control circuit comprises a clock supply circuit for supplying a first clock signal for said sampling circuit and a second close signal for the sequential comparison controller, the first and second clock signals having independently controlled respective frequencies.

Claim 11

An analog-to-digital converter comprising: a sampling circuit, which operates in accordance with first clock signal, for sampling an analog signal; a conversion circuit, which operates in accordance with a second clock signal, for converting the analog signal sampled by said sampling circuit to a digital signal; and a clock supply circuit for supplying the first and second clock signals and which varies, independently, the respective frequencies of the first and second clock signals in accordance with a control information.

Claim 12

An analog-to-digital converter comprising: a sampling circuit, which operates in accordance with first clock signal, for sampling an analog signal; a conversion circuit, which operates in accordance with a second clock signal, for converting the analog signal sampled by said sampling circuit to a digital signal; and a clock supply circuit for supplying the first and second clock signals and which varies, independently, the respective frequencies of the first and second clock signals in accordance with a control information.

Claim 13

An analog-to-digital converter, formed in a semiconductor substrate, comprising: a sampling circuit, which operates in accordance with a first clock signal, for sampling an analog signal; a conversion circuit, which operates in accordance with a second clock signal, for converting the sampled analog signal to a digital signal; a clock generating circuit for providing a plurality of clock signals having respective, different frequencies; and a wiring pattern affords selection of the first and second clock signals from the plurality of clock signals by a master-slice method.

Claim 14

An analog-to-digital converter, formed in a semiconductor substrate, comprising: a sampling circuit, which operates in accordance with a first clock signal, for sampling an analog signal; a conversion circuit, which operates in accordance with a second clock signal, for converting the sampled analog signal to a digital signal; a clock generating circuit for providing a plurality of clock signals having respective, different frequencies; and a wiring pattern affords selection of the first and second clock signals from the plurality of clock signals by a master-slice method.

Claim 15

A microcomputer, formed in a semiconductor substrate, comprising: a data processing unit; a data bus; control register means, connected to the data processing unit by the data bus and thereby accessible by said data processing unit, for storing control information; and an analog-to-digital converter comprising: a sampling circuit for sampling an analog signal during a sampling period; a conversion circuit, operatively connected to said sampling circuit, for converting the analog signal sampled by the sampling circuit to a digital signal during a conversion period and providing the digital signal to said data bus, and a control circuit, operatively connected to said sampling circuit, said converting circuit, and said control register means, for independently controlling the respective durations of the sampling period and the conversion period, in accordance with the control information.

Claim 16

A microcomputer, formed in a semiconductor substrate, comprising: a data processing unit; a data bus; control register means, connected to the data processing unit by the data bus and thereby accessible by said data processing unit, for storing control information; and an analog-to-digital converter comprising: a sampling circuit for sampling an analog signal during a sampling period; a conversion circuit, operatively connected to said sampling circuit, for converting the analog signal sampled by the sampling circuit to a digital signal during a conversion period and providing the digital signal to said data bus, and a control circuit, operatively connected to said sampling circuit, said converting circuit, and said control register means, for independently controlling the respective durations of the sampling period and the conversion period, in accordance with the control information.

Claim 17

A microcomputer, formed in a semiconductor substrate, comprising: a data processing unit; a data bus; a clock generating circuit providing a plurality of clock signals having respective, different frequencies, at least one of the clock signals being supplied to the data processing unit; and an analog-to-digital converter comprising: a sampling circuit, which operates in accordance with a first clock signal, for sampling an analog signal, a conversion circuit, which operates in accordance with a second clock signal, for converting the analog signal sampled by said sampling circuit to a digital signal and providing the digital signal to said data bus, and a selection circuit for selecting the first and second clock signals from the plurality of clock signals.

Claim 18

A microcomputer, formed in a semiconductor substrate, comprising: a data processing unit; a data bus; a clock generating circuit providing a plurality of clock signals having respective, different frequencies, at least one of the clock signals being supplied to the data processing unit; and an analog-to-digital converter comprising: a sampling circuit, which operates in accordance with a first clock signal, for sampling an analog signal, a conversion circuit, which operates in accordance with a second clock signal, for converting the analog signal sampled by said sampling circuit to a digital signal and providing the digital signal to said data bus, and a selection circuit for selecting the first and second clock signals from the plurality of clock signals.

Claim 19

A microcomputer according to claim 13, further comprising: control register means, connected to the data processing unit by the data bus and thereby accessible by said data processing unit, for storing control information, the selection circuit being controlled by the control information stored in the control register means.

Claim 20

A microcomputer according to claim 13, wherein said selection circuit comprises a wiring pattern which affords selection of the first and second clock signals for the plurality of clock signals by a master-slice method.