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Patent US5258329A successfully refreshed from Google Patents.
US5258329A
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US
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Method for manufacturing a multi-layered interconnection structure for a semiconductor IC structure
Assignee: Toshiba Corp
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Filing: 1992-02-06
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Granted: 1993-11-02
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Expires: 2012-02-06
Abstract
Abstract A semiconductor integrated circuit device and its manufacturing method are disclosed, the method comprising the steps of forming, over a semiconductor substrate, a first interconnection layer which involves a step-like surface, forming, over a first interconnection layer, an insulating layer and planarizing the surface of the second insulating layer, providing a plurality of via holes of different depths in the insulating layer reaching the first interconnection layer, subsequent to the step, implanting an impurity ion in the first interconnection layer such that an electronegativity in the first interconnection layer varies in accordance with the depths of the via holes, depositing a metal film in the via holes, and forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer by the deposited metal film in the via holes.
Inventors
- 👤 Hideki Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:37
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
207 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming, over a semiconductor substrate, a first interconnection layer including a first surface having a first height and a second surface having a second height; (2) forming, over the first interconnection layer, an insulating layer having a planar surface; (3) providing a first via hole in the insulating layer in correspondence with said first surface of the first interconnection layer and having a first depth reaching said first surface of the first interconnection layer, and a second via hole in the insulating layer in correspondence with said second surface of the first interconnection layer and having a second depth reaching said second surface of the first interconnection layer; (4) implanting an impurity ion into at least the first surface of the first interconnection layer through said first via hole such that an electronegativity of the first surface of the first interconnection layer is changed in accordance with the first depth of the first via hole; (5) depositing a metal film so as to fill the first and second via holes; and (6) forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer via the metal film.
Claim 2
Independent Claim
207 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming, over a semiconductor substrate, a first interconnection layer including a first surface having a first height and a second surface having a second height; (2) forming, over the first interconnection layer, an insulating layer having a planar surface; (3) providing a first via hole in the insulating layer in correspondence with said first surface of the first interconnection layer and having a first depth reaching said first surface of the first interconnection layer, and a second via hole in the insulating layer in correspondence with said second surface of the first interconnection layer and having a second depth reaching said second surface of the first interconnection layer; (4) implanting an impurity ion into at least the first surface of the first interconnection layer through said first via hole such that an electronegativity of the first surface of the first interconnection layer is changed in accordance with the first depth of the first via hole; (5) depositing a metal film so as to fill the first and second via holes; and (6) forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer via the metal film.
Claim 3
Dependent Claim
85 words
A method according to claim 1, wherein the step of providing the first and second via holes further includes the step of providing a third via hole through said insulating layer having a third depth reaching a third surface of the first interconnection layer such that the first depth of the first via hole is less than the second depth of the second via hole and the second depth of the second via hole is less than the third depth of the third via hole.
Claim 4
Dependent Claim
42 words
A method according to claim 1 or 2, wherein after the step of implanting the impurity ion, the electronegativity of the first surface of the first interconnection layer is greater than the electronegativity of the second surface of the first interconnection layer.
Claim 5
Dependent Claim
15 words
A method according to claim 1, wherein the impurity ion to be implanted contains boron.
Claim 6
Dependent Claim
15 words
A method according to claim 1, wherein the impurity ion to be implanted contains arsenic.
Claim 7
Dependent Claim
15 words
A method according to claim 1, wherein the impurity ion to be implanted contains phosphorus.
Claim 8
Dependent Claim
15 words
A method according to claim 1, wherein the impurity ion to be implanted contains hydrogen.
Claim 9
Dependent Claim
18 words
A method according to claim 1, wherein the step (5) is done by a vapor phase growth method.
Claim 10
Independent Claim
224 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming, over a semiconductor substrate, a first interconnection layer having a first surface having a first height and having a second surface having a second height; (2) forming, over said first interconnection layer, an insulating layer having a upper-most planar surface; (3) implanting an impurity ion into the first surface of the first interconnection layer through a portion of the upper-most planar surface of the insulating layer in correspondence with the first surface of the first interconnection layer; (4) providing a a first via hole in the insulating layer in correspondence with the first surface of the first interconnection layer and having a first depth reaching the first surface of the first interconnection layer and a second via hole in the insulating layer in correspondence with the second surface of the first interconnection layer and having a second depth reaching the second surface of the first interconnection layer; (5) depositing a metal film so as to fill the first and second via holes; and (6) forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer by the deposited metal film in the first and second via holes, the insulating layer being formed as an insulating interlayer between the first and second interconnection layers.
Claim 11
Independent Claim
224 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming, over a semiconductor substrate, a first interconnection layer having a first surface having a first height and having a second surface having a second height; (2) forming, over said first interconnection layer, an insulating layer having a upper-most planar surface; (3) implanting an impurity ion into the first surface of the first interconnection layer through a portion of the upper-most planar surface of the insulating layer in correspondence with the first surface of the first interconnection layer; (4) providing a a first via hole in the insulating layer in correspondence with the first surface of the first interconnection layer and having a first depth reaching the first surface of the first interconnection layer and a second via hole in the insulating layer in correspondence with the second surface of the first interconnection layer and having a second depth reaching the second surface of the first interconnection layer; (5) depositing a metal film so as to fill the first and second via holes; and (6) forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer by the deposited metal film in the first and second via holes, the insulating layer being formed as an insulating interlayer between the first and second interconnection layers.
References Cited (Backward Citations)
US4265935A
Cited
US5063175A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-01 | 1997-05-03 | 1997-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-01 | 2001-05-03 | 2001-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-01 | 2005-05-03 | 2005-11-02 | $7700.00 | Window Closed / Lapsed |