Method and apparatus for dispatching tasks requiring short-duration processor affinity

Claim 2

A computer implemented method for dispatching a task requiring short affinity for a resource-owning processor in a processor complex comprising the steps of: a) issuing an instruction on a first processor by said task, said instruction requiring a resource to complete execution, said resource not being available on said first processor; b) suspending execution of said task at a point of interruption after said issuing of said instruction, and enqueueing a task-related control block, associated with said task, on a processor-related queue associated with said resource-owning processor; and c) dequeueing said task-related control block from said processor-related queue, and resuming said task on said resource-owning processor at said point of interruption, said task thereafter being freely dispatchable within said processor complex without regard to said resource.

Claim 3

The method of claim 1, further comprising the step of: after said resuming of said task on said resource-owning processor, having said task force its own preemption so that it can subsequently be redispatched on another processor.

Claim 4

The method of claim 1 in which said resource is a cryptographic feature, and said instruction is a cryptographic instruction.

Claim 5

Computer apparatus for dispatching a task requiring short-duration affinity for a resource-owning processor in a processor complex comprising said resource-owning processor having an asymmetric resource and another processor not having said asymmetric resource, said apparatus comprising: a) an instruction capable of complete execution by said resource-owning processor, but not capable of complete execution by said another processor; b) interrupt means for interrupting a task containing said instruction when said instruction starts to execute on said another processor; c) task resumption mean scheduled to a processor-related queue associated with said resource-owning processor, said task resumption means resuming said task at said instruction on said resource-owning processor when said task resumption means is dispatched on said resource-owning processor; and d) dispatcher means for selecting and dispatching work units, including said task resumption means, enqueued on said processor-related queue or a global queue, said dispatcher means searching said processor-related queue before searching said global queue.

Claim 6

Computer apparatus for dispatching a task requiring short-duration affinity for a resource-owning processor in a processor complex comprising said resource-owning processor having an asymmetric resource and another processor not having said asymmetric resource, said apparatus comprising: a) an instruction capable of complete execution by said resource-owning processor, but not capable of complete execution by said another processor; b) interrupt means for interrupting a task containing said instruction when said instruction starts to execute on said another processor; c) task resumption mean scheduled to a processor-related queue associated with said resource-owning processor, said task resumption means resuming said task at said instruction on said resource-owning processor when said task resumption means is dispatched on said resource-owning processor; and d) dispatcher means for selecting and dispatching work units, including said task resumption means, enqueued on said processor-related queue or a global queue, said dispatcher means searching said processor-related queue before searching said global queue.

Claim 7

The apparatus of claim 4 further comprising preemption means for allowing said task to force its own preemption.

Claim 8

The apparatus of claim 5 in which said asymmetric resource is a cryptographic feature and said instruction means is a cryptographic instruction means.

Claim 9

The apparatus of claim 5 in which said task-resumption means is a non-preemptable system request block (SRB).

Claim 10

Computer apparatus for dispatching a task requiring short-duration affinity comprising: a) a resource-owning processor having an asymmetric resource; b) another processor, tightly coupled to said resource-owning processor, said another processor not having said asymmetric resource; c) an instruction capable of complete execution by said resource-owning processor, but not capable of complete execution by said another processor; d) interrupt means for interrupting a task containing said instruction when said instruction executes on said another processor; e) task resumption means, scheduled to a processor-related queue associated with said resource-owning processor, said task resumption means resuming said task at said instruction on said resource-owning processor when said task resumption means is dispatched on said resource-owning processor; and f) dispatcher means for selecting and dispatching work units, including said task resumption means, enqueued on said processor-related queue or a global queue, said dispatcher means searching said processor-related queue before searching said global queue.

Claim 11

Computer apparatus for dispatching a task requiring short-duration affinity comprising: a) a resource-owning processor having an asymmetric resource; b) another processor, tightly coupled to said resource-owning processor, said another processor not having said asymmetric resource; c) an instruction capable of complete execution by said resource-owning processor, but not capable of complete execution by said another processor; d) interrupt means for interrupting a task containing said instruction when said instruction executes on said another processor; e) task resumption means, scheduled to a processor-related queue associated with said resource-owning processor, said task resumption means resuming said task at said instruction on said resource-owning processor when said task resumption means is dispatched on said resource-owning processor; and f) dispatcher means for selecting and dispatching work units, including said task resumption means, enqueued on said processor-related queue or a global queue, said dispatcher means searching said processor-related queue before searching said global queue.

Claim 12

The apparatus of claim 8 further comprising preemption means for allowing said task to force its own preemption.

Claim 13

The apparatus of claim 9 in which said asymmetric resource is a cryptographic feature and said instruction means is a cryptographic instruction means.

Claim 14

The apparatus of claim 9 in which said task-resumption means is a non-preemptable system request block (SRB).