Circuit for decoding convolutional codes for executing the survivor path storage and reverse scanning stage of a Viterbi algorithm

Claim 2

A convolutional code decoding circuit for executing the stage of a Viterbi algorithm which involves reverse scanning of a plurality of paths of a trellis representing a diagram of possible transitions resulting from encoding by an encoder comprising ν flip-flops, each node of the trellis being represented by a word of N=2.sup.ν bits, said circuit selecting from a plurality of possible survivor paths that having the lowest metric, so as to reconstitute the trellis path determined during encoding and to recover the sequence of information bits causing said path to be adopted, said circuit comprising: a memory storing a plurality of said words of N=2.sup.ν bits and connected to the output of said memory, a cascade of ν groups of 2-in-1 multiplexers progressively combining the 2.sup.ν outputs of the memory into a single output, a D type flip-flop being provided at the output of each multiplexer, the single final flip-flop outputting in sequence the information bits representing the required path and the select signal for each multiplexer being the output of said final flip-flop.

Claim 3

A convolutional code decoding circuit for executing the stage of a Viterbi algorithm which involves reverse scanning of a plurality of paths of a trellis representing a diagram of possible transitions resulting from encoding by an encoder comprising ν flip-flops, each node of the trellis being represented by a word of N=2.sup.ν bits, said circuit selecting from a plurality of possible survivor paths that having the lowest metric, so as to reconstitute the trellis path determined during encoding and to recover the sequence of information bits causing said path to be adopted, said circuit comprising: a memory storing a plurality of said words of N=2.sup.ν bits in the form of N/M separately selectable blocks each of M bits where M is a submultiple of N in the form M=2.sup.μ, the outputs of each block being applied to a common bus M bits wide, a circuit for selecting one of said blocks of M bits and applying it to said bus, an M-in-1 multiplexer receiving on its input side the M bits supplied to said bus, a D flip-flop being provided between each bus line and the corresponding input of the multiplexer, and a series combination of D flip-flops connected to the output of the multiplexer, the final flip-flop of said series combination outputting sequentially the information bits representing the required path and the select signals of the multiplexer and the command signals of the selector circuit being the respective outputs of the successive flip-flops of said series combination.

Claim 4

A convolutional code decoding circuit for executing the stage of a Viterbi algorithm which involves reverse scanning of a plurality of paths of a trellis representing a diagram of possible transitions resulting from encoding by an encoder comprising ν flip-flops, each node of the trellis being represented by a word of N=2.sup.ν bits, said circuit selecting from a plurality of possible survivor paths that having the lowest metric, so as to reconstitute the trellis path determined during encoding and to recover the sequence of information bits causing said path to be adopted, said circuit comprising: a memory storing a plurality of said words of N=2.sup.ν bits in the form of N/M separately selectable blocks each of M bits where M is a submultiple of N in the form M=2.sup.μ, the outputs of each block being applied to a common bus M bits wide, a circuit for selecting one of said blocks of M bits and applying it to said bus, an M-in-1 multiplexer receiving on its input side the M bits supplied to said bus, a D flip-flop being provided between each bus line and the corresponding input of the multiplexer, and a series combination of D flip-flops connected to the output of the multiplexer, the final flip-flop of said series combination outputting sequentially the information bits representing the required path and the select signals of the multiplexer and the command signals of the selector circuit being the respective outputs of the successive flip-flops of said series combination.