Patent US5257236A successfully refreshed from Google Patents.
US5257236A
Expired / Lapsed
US
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Static RAM
Assignee: Creative Technology Ltd
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Filing: 1991-08-01
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Granted: 1993-10-26
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Expires: 2011-08-01
Abstract
Abstract An improved static memory is described which, when used in a dual port cache memory simplifies write cycles by providing latching of decoded address signals which are used in a subsequent memory cycle for writing. Improved logic is described which allows the propagation of data at the rate ƒ with timing signals of frequency 1/2ƒ. An improved sense amplifier which is isolated from the column lines is the array is used.
Inventors
- 👤 P. Owen Sharp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:22
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
82 words
A memory apparatus comprising: a dual port memory array having first and second data ports, and first and second select lines; address decoder means for decoding address signals and for providing decoded address signals, said decoded address signals being coupled to said first select lines; and, circuit means coupled to said second select lines for selectively providing said decoded address signals from said address decoder means, to said second select lines to access said memory array upon occurrence of a predetermined event.
Claim 2
Dependent Claim
82 words
A memory apparatus comprising: a dual port memory array having first and second data ports, and first and second select lines; address decoder means for decoding address signals and for providing decoded address signals, said decoded address signals being coupled to said first select lines; and, circuit means coupled to said second select lines for selectively providing said decoded address signals from said address decoder means, to said second select lines to access said memory array upon occurrence of a predetermined event.
Claim 3
Dependent Claim
34 words
The apparatus defined by claim 1 wherein said decoded address signals applied to said first select lines during a memory cycle n are applied to said second select lines during a memory cycle n+1.
Claim 4
Independent Claim
35 words
The apparatus defined by claims 1 or 2 wherein said memory array is part of a cache memory and wherein said predetermined event is a hit condition in said cache memory during a write cycle.
Claim 5
Dependent Claim
20 words
The apparatus defined by claim 3 wherein data to be written into said array is latched at said second ports.
Claim 6
Dependent Claim
88 words
A memory apparatus comprising: a dual port memory array having first and second data ports and first and second select lines; address decoder means for decoding address signals and for providing decoded address signals, said decoded address signals being coupled to said first select lines for accessing said array at said first port; and, a first latch coupled to said address decoder means for receiving and latching said decoded address signals, said first latch coupled to said second select lines for accessing said array at said second port.
Claim 7
Dependent Claim
88 words
A memory apparatus comprising: a dual port memory array having first and second data ports and first and second select lines; address decoder means for decoding address signals and for providing decoded address signals, said decoded address signals being coupled to said first select lines for accessing said array at said first port; and, a first latch coupled to said address decoder means for receiving and latching said decoded address signals, said first latch coupled to said second select lines for accessing said array at said second port.
Claim 8
Dependent Claim
32 words
The apparatus defined by claim 5 including a second latch coupled to said second port, for storing data to be written into cells in said array selected by said second select lines.
Claim 9
Dependent Claim
31 words
The apparatus defined by claim 6 wherein said decoded address signals in said first latch select cells in said array on said second select lines upon occurrence of a predetermined event.
Claim 10
Dependent Claim
37 words
The apparatus defined by claim 7 wherein upon occurrence of said predetermined event, said decoded address signal from a memory cycle n select cells in said array on said second select lines during the memory cycle (n+1).
Claim 11
Independent Claim
20 words
The apparatus defined by claims 5 or 7 wherein said decoded address signals represented selected word lines in said array.
Claim 12
Dependent Claim
102 words
A memory apparatus comprising: a dual port memory array having first and second data ports and first and second select lines; an address decoder for decoding address signals and for providing decoded address signals, said decoded address signals being coupled to said first select lines for accessing said memory array through said first data port; and, a first latch coupled to said address decoder for receiving and latching said decoded address signals, said first latch coupled to said second select lines for permitting said decoded address signals from said address decoder to selectively access said memory array through said second data port.
Claim 13
Dependent Claim
102 words
A memory apparatus comprising: a dual port memory array having first and second data ports and first and second select lines; an address decoder for decoding address signals and for providing decoded address signals, said decoded address signals being coupled to said first select lines for accessing said memory array through said first data port; and, a first latch coupled to said address decoder for receiving and latching said decoded address signals, said first latch coupled to said second select lines for permitting said decoded address signals from said address decoder to selectively access said memory array through said second data port.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-25 | 1997-04-26 | 1997-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-25 | 2001-04-26 | 2001-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-25 | 2005-04-26 | 2005-10-26 | $7700.00 | Window Closed / Lapsed |