Gate-to-drain overlapped MOS transistor fabrication process

Claim 1

A method for fabricating a gate-to-drain overlapped MOS transistor having a semiconductor substrate of a first conductivity type, diffusion regions of a second conductivity type isolated from each other by a channel region formed within the substrate, and a first conductive layer formed on a first gate insulation layer formed on the surface of said channel region, said first gate insulating layer extending over said diffusion regions, said method comprising steps of: (a) forming a first insulation layer over exposed surfaces of said first conductive layer and said first gate insulation layer, and forming a photoresist on said first insulation layer; (b) carrying out a first etching process to etchback said photoresist to expose a part of said first insulation layer, said part being that part of the first insulation layer that was formed on a top surface of said first conductive layer and on an upper portion of both sidewalls of said first conductive layer, and to etch said exposed part of said first insulation layer to expose an upper portion of said first conductive layer and to remove the remaining photoresist to expose the remaining portions of said first insulation layer; (c) forming a second conductive layer over said exposed remaining portions of said first insulation layer and over said exposed upper portion of said first conductive layer, and forming a second insulation layer over said second conductive layer; and (d) performing a second etching process by removing part of said second insulation layer and part of said second conductive layer until the top surface of said first conductive layer is exposed, and removing part of the remaining portions of said second insulation layer and part of remaining portions of said second conductive layer formed over said diffusion regions to form gate sidewall spacers having a conductive layer therein.

Claim 2

A method for fabricating a gate-to-drain overlapped MOS transistor having a semiconductor substrate of a first conductivity type, diffusion regions of a second conductivity type isolated from each other by a channel region formed within the substrate, and a first conductive layer formed on a first gate insulation layer formed on the surface of said channel region, said first gate insulating layer extending over said diffusion regions, said method comprising steps of: (a) forming a first insulation layer over exposed surfaces of said first conductive layer and said first gate insulation layer, and forming a photoresist on said first insulation layer; (b) carrying out a first etching process to etchback said photoresist to expose a part of said first insulation layer, said part being that part of the first insulation layer that was formed on a top surface of said first conductive layer and on an upper portion of both sidewalls of said first conductive layer, and to etch said exposed part of said first insulation layer to expose an upper portion of said first conductive layer and to remove the remaining photoresist to expose the remaining portions of said first insulation layer; (c) forming a second conductive layer over said exposed remaining portions of said first insulation layer and over said exposed upper portion of said first conductive layer, and forming a second insulation layer over said second conductive layer; and (d) performing a second etching process by removing part of said second insulation layer and part of said second conductive layer until the top surface of said first conductive layer is exposed, and removing part of the remaining portions of said second insulation layer and part of remaining portions of said second conductive layer formed over said diffusion regions to form gate sidewall spacers having a conductive layer therein.

Claim 12

A method for fabricating a gate-to-drain overlapped MOS transistor, comprising: forming diffusion regions of second conductivity type isolated from each other by a channel region formed within a semiconductor substrate of a first conductivity type; forming a first insulation layer over said diffusion regions and said channel regions; forming a first conductive layer having a first pattern on said first insulation layer and over said channel region; forming a second insulation layer over exposed surfaces of said first conductive layer and said first insulation layer, and forming a photoresist on said second insulation layer; etching said photoresist and said second insulation layer until there is only a portion of said second insulation layer remaining, said remaining portion of said second insulation layer comprising a part remaining on a lower section of both side walls of said first conductive layer and on said first insulation layer; forming a second conductive layer over said remaining portion of said second insulation layer and over exposed upper sections of both side walls and an exposed top surface of said first conductive layer and forming a third insulation layer over said second conductive layer; and etching portions of said third insulation layer and said second conductive layer to expose the top surface of said first conductive layer and a portion of a top surface of said second insulation layer, the remaining portions of said third insulation layer and said second conductive layer forming sidewall spacer regions for masking part of said diffusion regions, said remaining portion of said second conductive layer having a second pattern different than said first pattern of said first conductive layer.

Claim 13

A method for fabricating a gate-to-drain overlapped MOS transistor, comprising: forming diffusion regions of second conductivity type isolated from each other by a channel region formed within a semiconductor substrate of a first conductivity type; forming a first insulation layer over said diffusion regions and said channel regions; forming a first conductive layer having a first pattern on said first insulation layer and over said channel region; forming a second insulation layer over exposed surfaces of said first conductive layer and said first insulation layer, and forming a photoresist on said second insulation layer; etching said photoresist and said second insulation layer until there is only a portion of said second insulation layer remaining, said remaining portion of said second insulation layer comprising a part remaining on a lower section of both side walls of said first conductive layer and on said first insulation layer; forming a second conductive layer over said remaining portion of said second insulation layer and over exposed upper sections of both side walls and an exposed top surface of said first conductive layer and forming a third insulation layer over said second conductive layer; and etching portions of said third insulation layer and said second conductive layer to expose the top surface of said first conductive layer and a portion of a top surface of said second insulation layer, the remaining portions of said third insulation layer and said second conductive layer forming sidewall spacer regions for masking part of said diffusion regions, said remaining portion of said second conductive layer having a second pattern different than said first pattern of said first conductive layer.