Flesh correction circuit and method of flesh correction

Claim 2

A flesh correction method, comprising the steps of: (a) generating a first I-axis reference signal and a first Q-axis reference signal from a subcarrier signal; (b) demodulating a chrominance signal using said first I-axis reference signal and said first Q-axis reference signal thereby generating a first I-axis demodulated signal and a first Q-axis demodulated signal, respectively; (c) processing said first I-axis demodulated signal and said first Q-axis demodulated signal through a computation process thereby generating an original correction signal; (d) processing said original correction signal in such a manner that said original correction signal is regarded as valid during a predetermined period in said first I-axis demodulated signal, thereby generating a correction signal; (e) correcting phases of said first I-axis reference signal and said first Q-axis reference signal by an amount which is determined under the control of said correction signal to generate a second I-axis reference signal and a second Q-axis reference signal; and (f) demodulating said chrominance signal using said second I-axis reference signal and said second Q-axis reference signal thereby generating a second I-axis demodulated signal and a second Q-axis demodulated signal, respectively.

Claim 3

A method of claim 1, wherein said first I-axis reference signal is derived by phase-shifting said subcarrier signal; and said first Q-axis reference signal is derived by phase-shifting said first I-axis reference signal by 90 degrees.

Claim 4

A method of claim 1 wherein said computation process is multiplication.

Claim 5

A method of claim 1 wherein said step (d) comprises the steps of: (d-1) allowing said original correction signal to serve as said correction signal during a period in which said first I-axis demodulated signal stays at a potential equal to or higher than a predetermined bias potential; and (d-2) allowing said correction signal to be fixed at a predetermined fixed potential during a period in which said first I-axis demodulated signal stays at a potential lower than said predetermined bias potential.

Claim 6

A method of claim 4 wherein said bias potential is equal to or larger than a potential at a center point of the magnitude of said first I-axis demodulated signal.

Claim 7

A method of claim 5 wherein said fixed potential is equal to a potential at a center point of the magnitude of said original correction signal.

Claim 8

A method of claim 4 wherein said step (d) further comprises the step of (d-3) removing a high frequency component from said correction signal.

Claim 9

A method of claim 4 wherein, in said step (e), said first I-axis reference signal is phase-shifted by an amount corresponding to a potential which is determined in accordance with said correction signal on the basis of said fixed potential.

Claim 10

A method of claim 1, wherein said step (e) comprises the steps of: (e-1) phase-shifting said first I-axis reference signal so that said first I-axis reference signal has a phase lead of 45 degrees, whereby an I-axis leading waveform is generated; (e-2) phase-shifting said first I-axis reference signal so that said first I-axis reference signal has a phase delay of 45 degrees, whereby an I-axis delaying waveform is generated; and (e-3) synthesizing said I-axis leading waveform and said I-axis delaying waveform in a ratio which is determined in accordance with said amount of phase correction, whereby said second I-axis reference signal is generated.

Claim 11

A method of claim 9, wherein said step (e) further comprises the steps of: (e-4) phase-shifting said first Q-axis reference signal so that said first Q-axis reference signal has a phase lead of 45 degrees, whereby a Q-axis leading waveform is generated; (e-5) phase-shifting said first Q-axis reference signal so that said first Q-axis reference signal has a phase delay of 45 degrees, whereby a Q-axis delaying waveform is generated; and (e-6) synthesizing said Q-axis leading waveform and said Q-axis delaying waveform in a ratio which is determined in accordance with said amount of phase correction, whereby said second Q-axis reference signal is generated.

Claim 12

A flesh correction circuit, comprising: a first terminal at which a subcarrier signal is inputted; a second terminal at which a chrominance signal is inputted; a fixed phase shifter for generating a first I-axis reference signal and a first Q-axis reference signal from said subcarrier signal; a first I-axis demodulation circuit for demodulating said chrominance signal using said first I-axis reference signal and generating a first I-axis demodulated signal; a first Q-axis demodulation circuit for demodulating said chrominance signal using said first Q-axis reference signal and generating a first Q-axis demodulated signal; a computation circuit for processing said first I-axis demodulated signal and said first Q-axis demodulated signal through a computation process and generating an original correction signal; a signal generating circuit for processing said original correction signal in such a manner that said original correction signal is regarded as valid during a predetermined period in said first I-axis demodulated signal, thereby generating a correction signal; a variable phase shifter for correcting phases of said first I-axis reference signal and said first Q-axis reference signal by an amount which is determined under the control of said correction signal to generate a second I-axis reference signal and a second Q-axis reference signal; a second I-axis demodulation circuit for demodulating said chrominance signal using said second I-axis reference signal and generating a second I-axis demodulated signal; and a second Q-axis demodulation circuit for demodulating said chrominance signal using said second Q-axis reference signal and generating a second Q-axis demodulated signal.

Claim 13

A flesh correction circuit, comprising: a first terminal at which a subcarrier signal is inputted; a second terminal at which a chrominance signal is inputted; a fixed phase shifter for generating a first I-axis reference signal and a first Q-axis reference signal from said subcarrier signal; a first I-axis demodulation circuit for demodulating said chrominance signal using said first I-axis reference signal and generating a first I-axis demodulated signal; a first Q-axis demodulation circuit for demodulating said chrominance signal using said first Q-axis reference signal and generating a first Q-axis demodulated signal; a computation circuit for processing said first I-axis demodulated signal and said first Q-axis demodulated signal through a computation process and generating an original correction signal; a signal generating circuit for processing said original correction signal in such a manner that said original correction signal is regarded as valid during a predetermined period in said first I-axis demodulated signal, thereby generating a correction signal; a variable phase shifter for correcting phases of said first I-axis reference signal and said first Q-axis reference signal by an amount which is determined under the control of said correction signal to generate a second I-axis reference signal and a second Q-axis reference signal; a second I-axis demodulation circuit for demodulating said chrominance signal using said second I-axis reference signal and generating a second I-axis demodulated signal; and a second Q-axis demodulation circuit for demodulating said chrominance signal using said second Q-axis reference signal and generating a second Q-axis demodulated signal.

Claim 14

A circuit of claim 11 wherein said fixed phase shifter generates said first I-axis reference signal by phase-shifting said subcarrier signal by a predetermined amount and generates said first Q-axis reference signal by phase-shifting said subcarrier signal by the sum of 90 degrees plus said predetermined amount.

Claim 15

A circuit of claim 11 wherein said computation circuit is a multiplier.

Claim 16

A circuit of claim 11 wherein said signal generating circuit allows said original correction signal to serve as said correction signal during a period in which said first I-axis demodulated signal stays at a potential equal to or higher than a predetermined bias potential but requires said correction signal to be fixed at a predetermined fixed potential during a period in which said first I-axis demodulated signal stays at a potential lower than said predetermined bias potential.

Claim 17

A circuit of claim 14 wherein said predetermined bias potential is equal to or larger than a potential at a center point of the magnitude of said first I-axis demodulated signal.

Claim 18

A circuit of claim 15 wherein said fixed potential is equal to a potential at a center point of the magnitude of said original correction signal.

Claim 19

A circuit of claim 14 wherein said signal generating circuit comprises a low pass filter.

Claim 20

A circuit of claim 14 wherein said variable phase shifter phase-shifts said first I-axis reference signal by an amount corresponding to a potential which is determined in accordance with said correction signal on the basis of said fixed potential.

Claim 21

A circuit of claim 11, wherein said variable phase shifter comprises: a 45-degree phase shifting circuit for phase-shifting said first I-axis reference signal so that said first I-axis reference signal has a phase lead of 45 degrees thereby to generate an I-axis leading waveform and phase-shifting said first I-axis reference signal so that said first I-axis reference signal has a phase delay of 45 degrees thereby to generate an I-axis delaying waveform; and a synthesizing circuit for synthesizing said I-axis leading waveform and said I-axis delaying waveform in a ratio which is determined in accordance with said amount of phase correction, whereby said second I-axis reference signal is generated.

Claim 22

A circuit of claim 19 wherein said variable phase shifter further comprises: a 45-degree phase shifting circuit for phase-shifting said first Q-axis reference signal so that said first Q-axis reference signal has a phase lead of 45 degrees thereby to generate a Q-axis leading waveform and phase-shifting said first Q-axis reference signal so that said first Q-axis reference signal has a phase delay of 45 degrees thereby to generate a Q-axis delaying waveform; and a synthesizing circuit for synthesizing said Q-axis leading waveform and said Q-axis delaying waveform in a ratio which is determined in accordance with said amount of phase correction, whereby said second Q-axis reference signal is generated.