Integrated circuit having a sense amplifier

Claim 2

An integrated field-effect transistor memory circuit comprising memory cells which are arranged in rows and columns, each column of memory cells being connected to a bit line and a non-bit line by way of selection means, and also comprising at least one sense amplifier which comprises a first and a second input for coupling respectively to a bit line and an associated non-bit line of a column, each of which is coupled to a supply terminal via a load, which sense amplifier performs a current measurement on the first and the second input during the reading of information on the first and the second input, and which sense amplifier comprises a parallel connection of a first and a second current branch, each current branch comprising a control transistor having a gate, a source and a drain, the source of the control transistor in the first and the second current branch being connected to the first and the second input, respectively, characterized in that the sense amplifier also equalizes the voltages on the first and the second input during the current measurement, the gate of the control transistor in each current branch being connected to the drain of the control transistor in the other current branch, the channel of a load transistor, comprising a gate, a source and a drain, being connected between the drain of the relevant control transistor and a supply terminal in each current branch, said load transistor being of the same conductivity type as the control transistor in the relevant current branch, the coupled gates of said load transistors receiving a selection signal for the selective activation of the sense amplifier.

Claim 3

An integrated field-effect transistor memory circuit as claimed in claim 1, characterized in that the load transistor and the control transistor in each current branch are P-type transistors.

Claim 4

An integrated field-effect transistor memory circuit as claimed in claim 1, comprising a plurality of sense amplifiers which are connected to the same data bus at the output side, characterized in that between the data bus and a supply terminal there is included a field-effect transistor which is connected as a diode.

Claim 5

An integrated field-effect transistor memory circuit as claimed in claim 1, characterized in that a width/length ratio (W/L) of the load transistor in each current branch is substantially equal to the width/length ratio (W/L) of the control transistor.

Claim 6

An integrated circuit comprising driving means connected to a bit line and a non-bit line, the bit line and the non-bit line each being coupled to a first supply terminal via a load, and to a second supply terminal via a sense amplifier, the sense amplifier comprising a parallel connection of a first and second current branch, each current branch comprising a series arrangement of control transistor and a load transistor of the same conductivity type, respective sources of the control transistor in the first and the second current branch being coupled to the bit line and non-bit line respectively, the gate of the control transistor in each current branch being connected to the drain of the control transistor in the other current branch, channels of the respective load transistors in each current branch coupling the drain of the control transistor to the second supply terminal, the integrated circuit further comprising means for driving the gates of the load transistors so as to make the channels of the load transistors conduct during readout of the sense amplifier.

Claim 7

An integrated circuit comprising driving means connected to a bit line and a non-bit line, the bit line and the non-bit line each being coupled to a first supply terminal via a load, and to a second supply terminal via a sense amplifier, the sense amplifier comprising a parallel connection of a first and second current branch, each current branch comprising a series arrangement of control transistor and a load transistor of the same conductivity type, respective sources of the control transistor in the first and the second current branch being coupled to the bit line and non-bit line respectively, the gate of the control transistor in each current branch being connected to the drain of the control transistor in the other current branch, channels of the respective load transistors in each current branch coupling the drain of the control transistor to the second supply terminal, the integrated circuit further comprising means for driving the gates of the load transistors so as to make the channels of the load transistors conduct during readout of the sense amplifier.

Claim 8

An integrated circuit as claimed in claim 5, characterized in that the load transistor and the control transistor in each current branch are P-type transistors.

Claim 9

An integrated circuit as claimed in claim 5, characterized in that a width/length ratio (W/L) of the load transistor in each current branch is substantially equal to the width/length ratio (W/L) of the control transistor in that current branch.

Claim 10

An integrated circuit according to claim 5, in which the driving means comprises a plurality of memory cells of a field effect transistor memory, all memory cells from the plurality being connected to the bit line and the non-bit line by way of respective selection means.

Claim 11

An integrated circuit comprising driving means connected to a plurality of pairs of lines constituting a bit line and a non-bit line, the bit line and non-bit line from each pair each being coupled to a first supply terminal via a particular load, and to a second supply terminal via a particular sense amplifier to which the pair of lines corresponds, each particular sense amplifier comprising a parallel connection of a first and second current branch, each current branch comprising a series arrangement of a control transistor and a load transistor of the same conductivity type, respective sources of the control transistor in the first and the second current branch being coupled to the corresponding bit line and non-bit line respectively, the gate of the control transistor in each current branch of each particular sense amplifier being connected to the drain of the control transistor in the other current branch in the same particular sense amplifier, the channels of the load transistors in each particular sense amplifier coupling the drains of the control transistor in the first and second current branches of each sense amplifier respectively to a first and second conductor of a data bus, first and second field-effect transistors connected as diodes respectively coupling the first and second conductors of the data bus to the second power supply terminal, the integrated circuit further comprising means for driving the gates of the load transistors of a selected sense amplifier so as to make the channels of the load transistors of the selected sense amplifier conduct during readout of the selected sense amplifier via the data bus.

Claim 12

An integrated circuit comprising driving means connected to a plurality of pairs of lines constituting a bit line and a non-bit line, the bit line and non-bit line from each pair each being coupled to a first supply terminal via a particular load, and to a second supply terminal via a particular sense amplifier to which the pair of lines corresponds, each particular sense amplifier comprising a parallel connection of a first and second current branch, each current branch comprising a series arrangement of a control transistor and a load transistor of the same conductivity type, respective sources of the control transistor in the first and the second current branch being coupled to the corresponding bit line and non-bit line respectively, the gate of the control transistor in each current branch of each particular sense amplifier being connected to the drain of the control transistor in the other current branch in the same particular sense amplifier, the channels of the load transistors in each particular sense amplifier coupling the drains of the control transistor in the first and second current branches of each sense amplifier respectively to a first and second conductor of a data bus, first and second field-effect transistors connected as diodes respectively coupling the first and second conductors of the data bus to the second power supply terminal, the integrated circuit further comprising means for driving the gates of the load transistors of a selected sense amplifier so as to make the channels of the load transistors of the selected sense amplifier conduct during readout of the selected sense amplifier via the data bus.

Claim 13

An integrated circuit according to claim 9, in which the driving means comprises columns of rows of memory cells of a field effect transistor memory, each column corresponding to a particular sense amplifier, memory cells from each particular column being connected by way of selection means to the corresponding bit line and the non-bit line.