SRAM with an address and data multiplexer

Claim 2

A single chip latched SRAM device comprising: a memory array organized to store data in a word format with each word containing a predetermined number of data bits; address latch means having an address latch enable (ALE) input line, said latch means being responsive to an ALE input signal applied to said input line and operative to selectively couple a plurality of input address lines to said memory array for addressing particular locations in said memory array, said address latch means being functionally transparent when the input to said ALE input signal is of one state, and the output therefrom being latched when the ALE input signal is of a second state; data input/output means for selectively coupling a plurality of data input/output lines to said memory array and responsive to a control signal to determine when data is to be input thereto or output therefrom, one or more of said data input/output lines sharing common external connections with corresponding input address lines; and control logic means responsive to an output enable signal (G), chip enable signals (E 1 and E 2 ) and a write enable signal (V), and operative to develop said control signal for controlling said data input/output means such that when G is of one state and W is of one state, data from said memory array will be output to said input/ output lines, and when W is of a second state and e,ovs/G/ is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E 1 is of a first state and E 2 is of a first state, the device is selected, and when E 1 is of a second state and E 2 is of a second state, the device is deselected; wherein said address latch enable (ALE) input signal and said control signal are operative to determine whether the lines sharing common external connections function as input address lines or data input/output lines.

Claim 3

A single chip latched SRAM device as recited in claim 1 and further comprising: row decoder means and column decoder means associated with respective ones of said input address lines and operative to individually address selected word storage sites within said memory array.

Claim 4

A single chip latched SRAM device as recited in claim 2 and further comprising: column input/output means associated with said column decoder means and said data input/output means and operative to couple an addressed memory site to said input/output lines.

Claim 5

A single chip latched SRAM device as recited in claim 1, 2 or 3 wherein said device is packaged in a 28-pin TSOP package.

Claim 6

A single chip latched SRAM device as recited in claim 1, 2 or 3 wherein said device is packaged in a 28-pin SOG package.

Claim 7

In a microcontroller system including a microprocessor and memory means for storing processing data, an improved memory means embodied in one or more integrated circuit device each comprising: a memory array organized to store data in a word format with each word containing a predetermined number of data bits; address latch means having an address latch enable (ALE) input line, said latch means being responsive to an ALE input signal applied to said input line and operative to selectively couple a plurality of input address lines to said memory array for addressing particular locations in said memory array, said address latch means being functionally transparent when the input to said ALE input is of one state, and the output therefrom being latched when the ALE input is of a second state; data input/output means for selectively coupling a plurality of data input/output lines to said memory array and responsive to a control signal to determine when data is to be input thereto or output therefrom, one or more of said data input/output lines sharing common external connections with corresponding input address lines; and control logic means responsive to an output enable signal (G), chip enable signals (E 1 and E 2 ) and a write enable signal (W), and operative to develop said control signal for controlling said data input/output means such that when G is of one state and W is of one state, data from said memory array will be output to said input/output lines and when W is of a second state and G is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E 1 is of a first state and E 2 is of a first state, the device is selected, and when E 1 is of a second state and E 2 is of a second state, the device is deselected; wherein said address latch enable (ALE) input signal and said control signal are operative to determine whether the lines hearing common external connections function as input address lines or data input/output lines.

Claim 8

In a microcontroller system including a microprocessor and memory means for storing processing data, an improved memory means embodied in one or more integrated circuit device each comprising: a memory array organized to store data in a word format with each word containing a predetermined number of data bits; address latch means having an address latch enable (ALE) input line, said latch means being responsive to an ALE input signal applied to said input line and operative to selectively couple a plurality of input address lines to said memory array for addressing particular locations in said memory array, said address latch means being functionally transparent when the input to said ALE input is of one state, and the output therefrom being latched when the ALE input is of a second state; data input/output means for selectively coupling a plurality of data input/output lines to said memory array and responsive to a control signal to determine when data is to be input thereto or output therefrom, one or more of said data input/output lines sharing common external connections with corresponding input address lines; and control logic means responsive to an output enable signal (G), chip enable signals (E 1 and E 2 ) and a write enable signal (W), and operative to develop said control signal for controlling said data input/output means such that when G is of one state and W is of one state, data from said memory array will be output to said input/output lines and when W is of a second state and G is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E 1 is of a first state and E 2 is of a first state, the device is selected, and when E 1 is of a second state and E 2 is of a second state, the device is deselected; wherein said address latch enable (ALE) input signal and said control signal are operative to determine whether the lines hearing common external connections function as input address lines or data input/output lines.

Claim 9

In a microcontroller system as recited in claim 6 and further comprising: row decoder means and column decoder means associated with respective ones of said input address lines and operative to individually address selected word storage sites within each said memory array.

Claim 10

In a microcontroller system as recited in claim 7 and further comprising: column input/output means associated with said column decoder means and said data input/output means and operative to couple an addressed memory site to said input/output lines.

Claim 11

In a microcontroller system as recited in claim 8, wherein said memory means includes first and second integrated circuit devices, and said microprocessor generates a high order address signal which is connected as chip enable signal E 1 of said first integrated circuit device, and said high order address signal is also connected as chip enable signal E 2 of said second integrated circuit device, whereby said high order address signal functions to select which of said integrated circuit devices is active.

Claim 12

In a microcontroller system as recited in claim 6, 7, 8 or 9, wherein said integrated circuit devices are packaged in 28-pin TSOP packages.

Claim 13

In a microcontroller system as recited in claim 6, 7, 8 or 9, wherein said integrated circuit devices are packaged in 28-pin SOG packages.

Claim 14

A single chip latched SRAM device as recited in claims 1, 2 or 3 and further comprising: two or more external connections for power input; and two or more external connections for ground input.