Abstract The invention relates to a method and an arrangement for stabilizing a high-order sigma-delta modulator comprising at least two integrator stages and a quantizing means. The first, the first two or the first three integrator stages of the high-order modulator form a low-order modulator which is stable at all input signal values. The arrangement comprises a means for resetting the integrator stages following the low-order modulator when the stable operation range of the high-order modulator is exceeded. For an MF modulator the arrangement further comprises a coupling means for decoupling the output of the last integrator of the high-order modulator from the quantizing means and for coupling the output of said low-order modulator to the quantizing means simultaneously with the resetting.
An arrangement for stabilizing an MF-type high-order sigma-delta modulator comprising at least two integrator stages and a quantizing means to which the output of the last integrator stage is connected, wherein the first, the first two or the first three integrator stages in the high-order modulator form a lower-order modulator which is stable at all input signal values, the arrangement comprising a means for resetting the integrator stages following the lower-order modulator and a coupling means for decoupling the output of one of said series-connected integrator stages from the quantizing means and for coupling the output of said lower-order modulator to the quantizing means when the output voltage of said last integrator stage exceeds a predetermined threshold value corresponding to the upper limit of the stable operation range of the high-order modulator.
Claim 2
Dependent Claim
132 words
An arrangement for stabilizing an MF-type high-order sigma-delta modulator comprising at least two integrator stages and a quantizing means to which the output of the last integrator stage is connected, wherein the first, the first two or the first three integrator stages in the high-order modulator form a lower-order modulator which is stable at all input signal values, the arrangement comprising a means for resetting the integrator stages following the lower-order modulator and a coupling means for decoupling the output of one of said series-connected integrator stages from the quantizing means and for coupling the output of said lower-order modulator to the quantizing means when the output voltage of said last integrator stage exceeds a predetermined threshold value corresponding to the upper limit of the stable operation range of the high-order modulator.
Claim 3
Dependent Claim
40 words
An arrangement according to claim 1, wherein the coupling means recouples the output of the last integrator stage to the quantizing means with a predetermined delay after the output of the last integrator again falls below said predetermined threshold value.
Claim 4
Dependent Claim
25 words
An arrangement according to claim 2, wherein said predetermined delay is at least one clock cycle per each delaying integrator stage following said lower-order modulator.