Phase comparing and CMI/NRZ decoding apparatus

Claim 2

A phase comparing and CMI/NRZ decoding apparatus for decoding CMI data to NRZ data according to clock pulse transition in the center of the unit bit interval of incoming CMI(Code Mark Inversion) data comprising: a clock pulse generating means for generating in-phase and inverse-phase clock pulses compared with an incoming clock pulse; a data output means for outputting inverted data and non-inverted data relative with the incoming CMI data; a inter-transitions time interval information output means, connected to the clock pulse generating means and the data output means, for outputting information about the relations of the phase of the transition of the clock pulse and the phase of the center of the unit bit interval (UI) of the CMI data, and for outputting information about the presence or not of transition occurrence in the CMI data; a reference pulse generating means, connected to the clock pulse generating means and the inter-transitions time interval information output means, and upon occurring of the rising transition in the input CMI data, producing a pulse being triggered by rising transition or falling transition of the clock pulse from the clock pulse generating means and having a pulse width equivalent to 1/2 clock pulse period; a rising transition detecting and, 2-step half-period shifting means connected to the clock pulse generating means and the reference pulse generating means, and upon occuring of the rising transition in the CMI data, outputting a pulse being delayed twice in sequence by 1/2 clock pulse period relative to the output of the reference pulse generating means and having a pulse width equivalent to a half of the clock pulse period; a falling transition detecting and 3-step half-period shifting means connected to the clock pulse generating means and the inter-transitions time interval information output means and, upon occurring of the falling transition in the CMI data, outputting a pulse being delayed three times in sequence by 1/2 clock pulse period relative to the falling transition of a pulse produced by the inter-transitions time interval information output means and having a pulse width equivalent to a half of the clock pulse period; a CMI/NRZ decoding means, connected to the clock pulse generating means and the falling transition detecting and 3-step half-period shifting means, for decoding the CMI data to the NRZ data, and a code violation detecting means for detecting code violation in the CMI data, which is connected to the clock pulse generating means, the reference pulse generating means, the rising transition detecting and 2-step half-period shifting means, and the falling transition detecting and 3-step half-period shifting means.

Claim 3

The apparatus according to claim 1, wherein the clock pulse generating means comprises an ECL(Emitter-Coupled Logic) receiver.

Claim 4

The apparatus according to claim 1, wherein the data output means comprises an ECL receiver.

Claim 5

The apparatus according to claim 1 wherein the inter-transitions time interval information output means 3 comprises: a first D-type flip-flop having a clock input to which non-inverting data from the ECL receiver is inputted and having a data input to which a logic level "1" is inputted; a second D-type flip-flop having a data input connected to the output of the first D-type flip-flop and having a clock input to which an in-phase clock pulse is inputted; a third D-type flip-flop having a data input coupled to the output of the first D-type flip-flop and having a clock input to which an inverse-phase clock pulse is inputted; a first OR gate having two inputs respectively coupled to the Q outputs of the second and third D-type flip-flops and having an output coupled to the clear inputs of the first, second and third D-type flip-flops; a fourth D-type flip-flop having a clock input to which the inverting data is inputted and having a D input to which a logic level "1" is inputted; a fifth D-type flip-flop having a D input connected to the Q output of the fourth D-type flip-flop and having a clock input to which the in-phase clock pulse is inputted; a sixth D-type flip-flop having a D input connected to the Q output of the fourth D-type flip-flop and having clock input to which the inverse-phase clock pulse is applied; a second OR gate having two inputs respectively coupled to Q outputs of the fifth and sixth flip-flops and having an output coupled to clear inputs of the fourth, fifth and sixth D-type flip-flops; and a third OR gate having two inputs to which output signals from the first and fourth D-type flip-flops are inputted respectively.

Claim 6

The apparatus according to claim 1 wherein the reference pulse generating means comprises: a first OR gate having an input to which an output signal of the inter-transitions time interval information output means is applied and having an input to which a feedback signal is applied, a first D-type flip-flop having a data input coupled to the output of the first OR gate and having a clock input to which the in-phase clock pulse is applied, a second D-type flip-flop having a data input coupled to the output of the first OR gate and having a clock input to which the inverse-phase clock pulse is applied; and an AND gate having two inputs coupled to the outputs of the first and second D-type flip-flops respectively and having an output coupled to the clear inputs of the first and second D-type flip-flops, and a second OR gate having two inputs coupled to the Q outputs of the first and second D-type flip-flops respectively and having an output connected to one of the inputs of the first OR gate.

Claim 7

The apparatus according to claim 1, wherein the rising transition detecting and 2-step half-period shifting means comprises first and second half-period shifting circuits and wherein the first half-period shifting circuit comprises: a first OR gate having an input coupled to the output of the reference pulse generating means and having an input to which a feedback signal is applied, a first D-type flip-flop having a data input coupled to the output of the first OR gate and having a clock input to which the in-phase clock pulse is applied, a second D-type flip-flop having a data input coupled to the output of the reference pulse generating means and having a clock input to which the inverse-phase clock pulse is applied, a first AND gate having two inputs coupled to the Q outputs of the first and second D-type flip-flops respectively and having an output coupled to the clear inputs of the first and second D-type flip-flops; and a second OR gate having two inputs coupled to the Q outputs of the first and second D-type flip-flops and having an output coupled to the input of the first OR gate, and the second half-period shifting circuit comprises: a third OR gate having an input coupled to the output of the second OR gate and having an input to which a feedback signal is applied, a third D-type flip-flop having a data input coupled to the output of the third OR gate and having a clock input to which the in-phase clock pulse is applied, a fourth D-type flip-flop having a data input coupled the output of the third OR gate and having a clock input to which the inverse-phase clock pulse is applied, a second AND gate having two inputs coupled to the outputs of the third and fourth D-type flip-flops respectively and having an output coupled to the clear inputs of the third and fourth D-type flip-flops, and a fourth OR gate having two inputs coupled to the outputs of the third and second D-type flip-flop respectively and having an output coupled to the input of the third OR gate.

Claim 8

The apparatus according to claim 1, wherein the falling transition detecting and 3-step half-period shifting means comprises; first, second and third half-period shifting circuits, and wherein the first half-period shifting circuit comprises: a first OR gate having an input coupled to the output of the inter-transitions time interval information output means and having an input to which a feedback signal is applied, a first D-type flip-flop having a data input coupled to the output of the first OR gate and having a clock input to which the in-phase clock pulse is applied, a second D-type flip-flop having a data input coupled to the output of the first OR gate and having a clock input to which the inverse-phase clock pulse is applied, a first AND gate having two inputs coupled to the outputs of the first and second D-type flip-flops respectively and having an output coupled to the clear inputs of the first and second D-type flip-flops, and a second OR gate having two inputs coupled to the outputs of the first and second D-type flip-flops respectively and an output coupled to the input of the first OR gate, and the second half-period shifting circuit comprises: a third OR gate having an input coupled to the output of the second OR gate and having an input to which a feedback signal is applied, a third D-type flip-flop having a data input coupled to the output of the third OR gate and having a clock input to which the in-phase clock pulse is applied, a fourth D-type flip-flop having a data input coupled to the output of the third OR gate and a clock input to which the inverse-phase clock pulse is applied, a second AND gate having two inputs coupled to the outputs of the third and fourth D-type flip-flops respectively and an output coupled to the clear inputs of the third and fourth D-type flip-flops, and a fourth OR gate having two inputs coupled to the output of the third and fourth D-type flip-flops respectively and an output coupled to the input of the third OR gate, and the third half-period shifting circuit comprises: a fifth OR gate having an input coupled to the output of the fourth OR gate and having an input to which a feedback signal is applied, a fifth D-type flip-flop having a data input coupled to the output of the fifth OR gate and having a clock input to which the in-phase clock pulse is applied, a sixth D-type flip-flop having a data input coupled to the output of the fifth OR gate and a clock input to which the inverse-phase clock pulse is applied, a third AND gate having two inputs coupled to the outputs of the fifth and sixth D-type flip-flops respectively and an output coupled to the clear inputs of the fifth and sixth D-type flip-flops, and a sixth OR gate having two inputs coupled to the outputs of the fifth and sixth D-type flip-flops respectively and an output coupled to the input of the fifth OR gate.

Claim 9

The apparatus according to claim 1, wherein the CMI/NRZ decoding means comprises: a first NOR gate having two inputs coupled to the output of the rising transition detecting and 2-step half-period shifting means and the output of the second half-period shifting circuit in falling transition detecting and 3-step half-period shifting means respectively, a second NOR gate having three inputs one of which being coupled to the output of the rising transition detecting and 2-step half-period shifting means and remaining two inputs being coupled to the outputs of the fast and second half-period shifting circuits in the falling transition detecting and 3-step half-period shifting means respectively, a OR gate having two inputs coupled to the outputs of the first and second NOR gate respectively, a first D-type flip-flop having a data input coupled to the output of the OR gate and having a clock input coupled to which the in-phase clock pulse is applied, a second D-type flip-flop having a data input coupled to the output of the OR gate and having a clock input to which the inverse-phase clock pulse is applied, a third NOR gate having two inputs coupled to the outputs of the first and second D-type flip-flop respectively, and a third D-type flip-flop having a data input coupled to the output of the third NOR gate and having a clock input to which the in-phase clock pulse is applied.

Claim 10

The apparatus according to claim 1 wherein the code violation detecting means comprises: a NOR gate having an input coupled to the output of the reference pulse generating means and having two inputs coupled to the two outputs of the rising tiansition detecting and 2-step half-period shifting means respectively, and also having three inputs coupled to the three outputs of the falling transition detecting and 3-step half-period shifting means respectively, a first D-type flip-flop having a data input coupled to the output of the NOR gate and having a clock input to which the in-phase clock pulse is applied, a second D-type flip-flop having a data input coupled to the output of the NOR gate and having a clock input to which the inverse-phase clock pulse is applied, a OR gate having two inputs coupled to the outputs of the first and second D-type flip-flop respectively, and a third D-type flip-flop having a data input coupled to the output of the OR gate and having a clock input to which the in-phase clock pulse is applied.