US5247685A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interrupt handling in an asymmetric multiprocessor computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-12-23
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Granted: 1993-09-21
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Expires: 2012-12-23
Abstract
Abstract Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.
Inventors
- 👤 John A. Landry
- 👤 Paul R. Culley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
258 words
An interrupt control system for a multiprocessor computer system including a first and a second processor operating asymmetrically with respect to each other, each processor sharing a bus and performing an interrupt acknowledge cycle on the bus in response to a processor interrupt signal received by the processor, the computer system further including means for generating interrupt signals intended for the first processor and means for generating an interrupt signal intended for the second processor and providing the processor interrupt signal to the second processor, the interrupt control system comprising: means for coupling to the bus for receiving the interrupt signals intended for the first processor and for providing a processor interrupt signal to the first processor means for coupling to the bus for placing; an interrupt vector on the bus when an interrupt acknowledge cycle is performed on the bus; means for coupling to the bus for determining if the second processor is controlling the bus; means coupled to said interrupt vector placing means and said second processor bus control determining means and for coupling to the bus for inhibiting said interrupt vector placing means from placing said interrupt vector on the bus if the second processor is controlling the bus when an interrupt acknowledge cycle is performed on the bus; and vector replacement logic means coupled to said means for inhibiting and said second processor bus control determining means and for coupling to the bus for providing a replacement interrupt vector for the second processor when said means for inhibiting inhibits said interrupt vector placing means.
Claim 2
Dependent Claim
258 words
An interrupt control system for a multiprocessor computer system including a first and a second processor operating asymmetrically with respect to each other, each processor sharing a bus and performing an interrupt acknowledge cycle on the bus in response to a processor interrupt signal received by the processor, the computer system further including means for generating interrupt signals intended for the first processor and means for generating an interrupt signal intended for the second processor and providing the processor interrupt signal to the second processor, the interrupt control system comprising: means for coupling to the bus for receiving the interrupt signals intended for the first processor and for providing a processor interrupt signal to the first processor means for coupling to the bus for placing; an interrupt vector on the bus when an interrupt acknowledge cycle is performed on the bus; means for coupling to the bus for determining if the second processor is controlling the bus; means coupled to said interrupt vector placing means and said second processor bus control determining means and for coupling to the bus for inhibiting said interrupt vector placing means from placing said interrupt vector on the bus if the second processor is controlling the bus when an interrupt acknowledge cycle is performed on the bus; and vector replacement logic means coupled to said means for inhibiting and said second processor bus control determining means and for coupling to the bus for providing a replacement interrupt vector for the second processor when said means for inhibiting inhibits said interrupt vector placing means.
Claim 3
Dependent Claim
49 words
The interrupt control system of claim 1, wherein said interrupt receiving means includes an integrated system peripheral receiving the interrupt signals intended for the first processor, masking selected ones of said received interrupt signals and providing processor interrupt signal to the first processor for each unmasked received interrupt signal.
Claim 4
Dependent Claim
88 words
The interrupt control system of claim 2, wherein said integrated system peripheral further includes said vector placing means, wherein said integrated system peripheral monitors cycles appearing on the bus when said interrupt receiving means is coupled to the bus, said integrated system peripheral detecting the start of each bus cycle and determining if an interrupt acknowledge cycle is being performed and placing an interrupt vector on the bus at the proper time after the start of the next bus cycle in response to said interrupt acknowledge cycle determination.
Claim 5
Dependent Claim
45 words
The interrupt control system of claim 3, wherein said means for inhibiting inhibits said integrated system peripheral from detecting the start of the next bus cycle following an interrupt acknowledge cycle determination by said integrated system peripheral when the second process is controlling the bus.
Claim 6
Dependent Claim
43 words
The interrupt control system of claim 4, wherein said vector replacement logic means monitors said means for inhibiting and provides said replacement interrupt vector at the proper time in the cycle during which said means for inhibiting is inhibiting said integrated system peripheral.
Claim 7
Dependent Claim
27 words
The interrupt control system of claim 1, wherein said vector replacement logic means includes means for receiving a replacement vector value from a processor over the bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |