EP0192944A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processing system with a main processor and a co-processor sharing the same resources
Assignee: International Business Machines Corp
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Filing: 1986-01-17
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Granted: —
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Expires: 2006-01-17
Abstract
Abstract Data processing system including a main processor (11) and a co-processor (22) sharing the same l/O facilities (17,18,19) as the main processor (11) and running software unknown to the main processor (11). The main processor (11) can concurrently run other software and maintains priority over shared 1/0 facilities (17,18,19) by providing trapping logic incorporated in a random access memory and dynamically loadable by the main processor (11) which contains data related to the current useability by the co-processor (22) of a shared l/O device (17). Additional logic is associated with the co-processor (22) to manage interrupts between the co-processor (22) and the system bus ( 16 ).
Inventors
- 👤 John William Irvin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 10:25
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G06F13/38; G06F13/382; G06F13/387; G06F15/00; G06F15/16; G06F15/161
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
97 words
Data processing system including a main processor and a co-processor sharing the utilization of at least one input/output device connected to a bus, said co-processor running software unknown to the main processor ; said system being characterized in that it comprises : first means dynamically controllable by said main processor for selectively preventing direct access to said input/output device by said co-processor; and second means for utilizing said main processor to service an attempted access of said input/output device when said first means has been enabled to prevent direct access to said input/output device by said co-processor.
Claim 2
Dependent Claim
97 words
Data processing system including a main processor and a co-processor sharing the utilization of at least one input/output device connected to a bus, said co-processor running software unknown to the main processor ; said system being characterized in that it comprises : first means dynamically controllable by said main processor for selectively preventing direct access to said input/output device by said co-processor; and second means for utilizing said main processor to service an attempted access of said input/output device when said first means has been enabled to prevent direct access to said input/output device by said co-processor.
Claim 3
Dependent Claim
19 words
The data processing system of Claim 1 wherein said input/output device further is a real or emulated input/output device.
Claim 4
Dependent Claim
23 words
The data processing system of Claim 1 or 2 wherein said first means further comprises means for disconnecting said co-processor from said bus.
Claim 5
Dependent Claim
24 words
The data processing system of Claim 1,2 or 3 wherein said second means further comprises means for saving an address of said input/output device.
Claim 6
Dependent Claim
23 words
The data processing system of Claim 4 wherein said second means further comprises means for issuing an interrupt signal to said main processor.
Claim 7
Dependent Claim
36 words
The data processing system of Claim 5 wherein said second means further comprises means for causing said main processor to access said input/output device corresponding to said saved address and read data from said input/output device.
Claim 8
Dependent Claim
47 words
The data processing system of Claim 6 wherein said second means further comprises means for causing said co-processor to be temporarily reconnected to a portion of said bus and means for causing said main processor to communicate said data read from said input/output device to said co-processor.
Claim 9
Dependent Claim
21 words
- The data processing system of Claim 7 wherein said portion of said bus is a data portion of said bus.
Claim 10
Dependent Claim
36 words
The data processing system of Claim 6 wherein said second means further comprises means for causing said main processor to access said input/output device corresponding to said saved address and write data to said input/output device.
Claim 11
Dependent Claim
48 words
The data processing system of Claim 9 wherein said second means further comprises means for causing said co-processor to be temporarily reconnected to a portion of said bus and means for causing said co-processor to communicate said data to be written from said co-processor to said main processor.
Claim 12
Dependent Claim
20 words
The data processing system of Claim 10 wherein said portion of said bus is a data portion of said bus.
Claim 13
Dependent Claim
31 words
The data processing system of any one of the preceding claims further comprising means controllable by said main processor for selectively preventing an interrupt on said bus from reaching said co-processor.
Claim 14
Dependent Claim
39 words
The data processing system of Claim 12 further comprising means controllable by said main processor for creating an interrupt from data on a data portion of said bus and causing this created interrupt to be sent to said co-processor.
References Cited (Backward Citations)
No citation records indexed.
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