US5247642A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for determining cacheability of a memory address to provide zero wait state operation in a computer system
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-12-05
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Granted: 1993-09-21
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Expires: 2010-12-05
Abstract
Abstract A computer system includes an Intel 80486 microprocessor having an internal cache memory and a local memory tightly coupled to the microprocessor that can respond to memory accesses without requiring the microprocessor to execute a wait state. An external cache memory system is provided to provide additional cache storage to provide copy back capabilities so that data written to the external cache does not have to be automatically written to slower bulk memory. The computer system includes a conventional Industry Standard Architecture bus (ISA-bus) which may include memory on the bus. The computer system may also include an external math coprocessor. In order to preclude storing data from the math coprocessor and from the ISA-bus memory, the external cache memory system includes a cache determination circuit that selectively generates a cache enable signal to the microprocessor and to the external cache memory system so that only cacheable data is stored in the two caches. The cache determination circuit operates sufficiently fast that when the microprocessor addresses a zero-wait state device, such as the external math coprocessor or the local memory, a cache enable signal is generated within the first clock cycle so that the local memory can respond within the second clock cycle without requiring a microprocessor wait state and the cache enable signal is not generated if the math coprocessor is addressed.
Inventors
- 👤 Kenneth A. Kadlec
- 👤 Shmuel Shottan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:47
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G06F12/0893; G06F12/0897; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
756 words
A computer system comprising: a microprocessor having an internal cache memory system, said microprocessor generating an address including a plurality of address bits, said address defining a storage location from which to store or retrieve data, said plurality of bits being sufficient to define at least first, second and third ranges of addresses, wherein said third range of addressed is included within said second range of addresses, said microprocessor outputting said address to an address bus during a first clock cycle and outputting an address valid signal to indicate that said address has been output to said address bus, said microprocessor responsive to a ready signal during a second clock cycle to input data from a data bus, aid internal cache memory system responsive to a cache enable signal to store said data in said internal cache memory system if said cache enable signal is active one clock cycle prior to said ready signal; a first data source that provides data to said microprocessor in response to said address from said microprocessor when said address is in said first range of addresses, said first data source receiving said address valid signal from said microprocessor, said first data source responsive to said address valid signal to output data to said data bus and to output said ready signal to said microprocessor in said second clock cycle, wherein said second clock cycle is a clock cycle immediately following said first clock cycle, so that said microprocessor does not have to wait for said data from said first data source, said data output to said data bus by said first data source including cacheable data to be stored in said internal cache memory system of said microprocessor; a second data source that provides data to said microprocessor in response to said address from said microprocessor when said address is in said second range of addresses, said second data source receiving said address valid signal from said microprocessor, said second data source responsive to said address valid signal to output data to said data bus and to output said ready signal to said microprocessor in said second clock cycle, wherein said second clock cycle is said clock cycle immediately following said first clock cycle, so that said microprocessor does not have to wait for said data from said second data source, said data output to said data bus from said second data source including non-cacheable data that is not stored in said internal cache memory system of said microprocessor; a third data source that provides data to said microprocessor in response to said address when said address is in said third range of addresses, said third data source receiving said address valid signal from said microprocessor, said third data source responsive to said address valid signal to output data to said data bus and to output said ready signal to said microprocessor in said second clock cycle, wherein said second clock cycle is a clock cycle that occurs subsequent to said clock cycle immediately following said first clock cycle, so that said microprocessor has to wait at least one clock cycle for said data from said third data source, said data output to said data bus from said third data source including non-cacheable data that is not stored in said internal cache memory system of said microprocessor; and a cache control signal generator responsive to said first, second and third ranges of addresses, said generator generating an active cache enable signal by the end of said first clock cycle when said generator receives said address from said microprocessor when said address is in said first range of addresses so that data is stored in said internal cache memory system of said microprocessor if said first clock data source generates a data ready during said clock cycle immediately following said first clock cycle, said generator deactivating said cache enable signal subsequent to the end of said first clock cycle and prior to the generation of said ready signal by said third data source when said generator receives said address from said microprocessor when said address is within said third range of addresses so that data from said third data source is not stored by said internal cache memory system of said microprocessor, said generator generating an inactive cache enable signal prior to the end of said first clock cycle when said microprocessor generates said address within said second range of addresses so that data from said second data source is not stored by said internal cache memory system of said microprocessor.
Claim 2
Dependent Claim
756 words
A computer system comprising: a microprocessor having an internal cache memory system, said microprocessor generating an address including a plurality of address bits, said address defining a storage location from which to store or retrieve data, said plurality of bits being sufficient to define at least first, second and third ranges of addresses, wherein said third range of addressed is included within said second range of addresses, said microprocessor outputting said address to an address bus during a first clock cycle and outputting an address valid signal to indicate that said address has been output to said address bus, said microprocessor responsive to a ready signal during a second clock cycle to input data from a data bus, aid internal cache memory system responsive to a cache enable signal to store said data in said internal cache memory system if said cache enable signal is active one clock cycle prior to said ready signal; a first data source that provides data to said microprocessor in response to said address from said microprocessor when said address is in said first range of addresses, said first data source receiving said address valid signal from said microprocessor, said first data source responsive to said address valid signal to output data to said data bus and to output said ready signal to said microprocessor in said second clock cycle, wherein said second clock cycle is a clock cycle immediately following said first clock cycle, so that said microprocessor does not have to wait for said data from said first data source, said data output to said data bus by said first data source including cacheable data to be stored in said internal cache memory system of said microprocessor; a second data source that provides data to said microprocessor in response to said address from said microprocessor when said address is in said second range of addresses, said second data source receiving said address valid signal from said microprocessor, said second data source responsive to said address valid signal to output data to said data bus and to output said ready signal to said microprocessor in said second clock cycle, wherein said second clock cycle is said clock cycle immediately following said first clock cycle, so that said microprocessor does not have to wait for said data from said second data source, said data output to said data bus from said second data source including non-cacheable data that is not stored in said internal cache memory system of said microprocessor; a third data source that provides data to said microprocessor in response to said address when said address is in said third range of addresses, said third data source receiving said address valid signal from said microprocessor, said third data source responsive to said address valid signal to output data to said data bus and to output said ready signal to said microprocessor in said second clock cycle, wherein said second clock cycle is a clock cycle that occurs subsequent to said clock cycle immediately following said first clock cycle, so that said microprocessor has to wait at least one clock cycle for said data from said third data source, said data output to said data bus from said third data source including non-cacheable data that is not stored in said internal cache memory system of said microprocessor; and a cache control signal generator responsive to said first, second and third ranges of addresses, said generator generating an active cache enable signal by the end of said first clock cycle when said generator receives said address from said microprocessor when said address is in said first range of addresses so that data is stored in said internal cache memory system of said microprocessor if said first clock data source generates a data ready during said clock cycle immediately following said first clock cycle, said generator deactivating said cache enable signal subsequent to the end of said first clock cycle and prior to the generation of said ready signal by said third data source when said generator receives said address from said microprocessor when said address is within said third range of addresses so that data from said third data source is not stored by said internal cache memory system of said microprocessor, said generator generating an inactive cache enable signal prior to the end of said first clock cycle when said microprocessor generates said address within said second range of addresses so that data from said second data source is not stored by said internal cache memory system of said microprocessor.
Claim 3
Dependent Claim
90 words
The computer system as defined in claim 1, wherein said first address range and said second address range are distinguishable by a single one of said address bits so that said cache control signal generator generates an active cache enable signal prior to the end of said first clock cycle when said single one of said address bits has a first state and generates an inactive cache enable signal prior to the end of said first clock cycle when said single one of said address bits has a second state.
Claim 4
Dependent Claim
73 words
The computer system as defined in claim 2, wherein said third address range within said first address range is decoded by said cache control signal generator from a plurality of address bits, and wherein said cache control signal generator requires an amount of time to decode said plurality of address bits such hat said cache control signal generator finishes decoding said plurality of address bits after the end of said first clock cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |