US5247476A
Expired / Lapsed
US
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Semiconductor memory device having a mask rom and a prom
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1990-09-18
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Granted: 1993-09-21
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Expires: 2010-09-18
Abstract
Abstract A semiconductor memory device with a mask ROM and a PROM whose program characteristics are different is provided with a switching means. The switching operation is performed so that the content of the mask ROM becomes effective when the mask ROM is programmed and so that the content of the PROM becomes effective when the RPOM is programmed. Thereby, both mask ROM and PROM become programmable, making the semiconductor memory device with mask ROM and PROM effectively operative.
Inventors
- 👤 Yasushi Kasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:13
CPC Classifications
G; G06; G06F; G06F12/00; G11; G11C; G11C11/00; G11C11/005; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G11C17/00; G11C17/08; G11C17/10
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
107 words
A semiconductor memory device comprising: a first ROM being in an ON state when said first ROM is programmed and a second ROM being in an OFF state when said second ROM is programmed; switching means for switching a current path for selectively reading contents of one of said first ROM and said second ROM, said contents stored as one of an ON state and an OFF state; and means for selectively reading the content of said first ROM when said first ROM is programmed under control of said switching means and for selectively reading the content of said second ROM when said second ROM is programed.
Claim 2
Dependent Claim
107 words
A semiconductor memory device comprising: a first ROM being in an ON state when said first ROM is programmed and a second ROM being in an OFF state when said second ROM is programmed; switching means for switching a current path for selectively reading contents of one of said first ROM and said second ROM, said contents stored as one of an ON state and an OFF state; and means for selectively reading the content of said first ROM when said first ROM is programmed under control of said switching means and for selectively reading the content of said second ROM when said second ROM is programed.
Claim 3
Dependent Claim
57 words
The semiconductor memory device according to claim 1, wherein said first ROM and said second ROM are connected in parallel through said switching means and said device further comprises a reading means, connected to a connection point connecting said switching means and said first ROM, for detecting whether said first ROM or said second ROM is programmed.
Claim 4
Dependent Claim
59 words
The semiconductor memory device according to claim 1, wherein said first ROM and said second ROM are connected in series and said first ROM is connected in parallel with said switching means and said device further comprises reading means, connected to a terminal of said second ROM, for detecting whether said first ROM or said second ROM is programmed.
Claim 5
Dependent Claim
39 words
The semiconductor memory device according to claim 3, wherein said first ROM comprises an enhancement type transistor and is programmed by making said enhancement type transistor into a depletion type transistor by injecting ions into said enhancement type transistor.
Claim 6
Dependent Claim
31 words
The semiconductor memory device according to claim 3, wherein said first ROM has a contact unit for programming said first ROM when said contact unit is switched to an active state.
Claim 7
Dependent Claim
35 words
The semiconductor memory device according to claim 3, wherein said first ROM has an insulating area, said first ROM being programmed by forming an impurity diffusion layer in said insulating area by injecting ions therein.
Claim 8
Dependent Claim
37 words
The semiconductor memory device according to claim 3, wherein said second ROM comprises an EPROM transistor and a charge is injected into a floating gate of said EPROM transistor, thereby enabling said EPROM transistor to be programmed.
Claim 9
Dependent Claim
28 words
The semiconductor memory device according to claim 3, wherein said second ROM comprises a fuse and the fuse is cut, thereby enabling said second ROM to be programmed.
Claim 10
Dependent Claim
56 words
The semiconductor memory device according to claim 1, wherein said first ROM and said second ROM are connected in parallel through said switching means and said device further comprises reading means, connected to a connection point connecting said switching means and said second ROM, for detecting whether said first ROM or said second ROM is programmed.
Claim 11
Dependent Claim
42 words
The semiconductor memory device according to claim 1, wherein said switching means is electrically connected to one of said first ROM and said second ROM by a switching signal supplied from a third ROM of a same type as said first ROM.
Claim 12
Dependent Claim
30 words
The semiconductor memory device according to claim 10, wherein said switching means comprises a transistor which turns on or off based on the switching signal supplied from said third ROM.
Claim 13
Dependent Claim
23 words
The semiconductor memory device according to claim 1, wherein said first ROM comprises a mask ROM and said second ROM comprises a PROM.
Claim 14
Dependent Claim
29 words
The semiconductor memory device according to claim 1, wherein said first and second ROM and said switching means forming a unit and wherein a plurality of units are provided.
Claim 15
Dependent Claim
86 words
A semiconductor memory device comprising: a first ROM being in an OFF state when said first ROM is programmed and a second ROM being in an ON state when said second ROM is programmed; switching means for programing said first ROM and said second ROM based on switching signals; and means for selectively reading content of said first ROM when said first ROM is programmed under control of said switching means and for selectively reading content of said second ROM when said second ROM is programmed.
Claim 16
Dependent Claim
86 words
A semiconductor memory device comprising: a first ROM being in an OFF state when said first ROM is programmed and a second ROM being in an ON state when said second ROM is programmed; switching means for programing said first ROM and said second ROM based on switching signals; and means for selectively reading content of said first ROM when said first ROM is programmed under control of said switching means and for selectively reading content of said second ROM when said second ROM is programmed.
Claim 17
Dependent Claim
59 words
The semiconductor memory device according to claim 14, wherein said first ROM and said second ROM are connected in series and said switching means is connected in parallel with said second ROM and said device further comprises reading means, connected to a terminal of said first ROM, for detecting whether said first ROM or said second ROM is programmed.
Claim 18
Dependent Claim
40 words
The semiconductor memory device according to claim 15, wherein said first ROM comprises a transistor and is programmed by increasing a threshold voltage of said transistor by injecting ions into said transistor, therein performing an ion implantation into said transistor.
Claim 19
Dependent Claim
26 words
The semiconductor memory device according to claim 15, wherein said second ROM has a PN junction unit and is programmed by destroying said PN junction unit.
Claim 20
Dependent Claim
38 words
The semiconductor memory device according to claim 15, wherein said second ROM has an insulation layer and is programmed by making said insulation layer non-insulating therein switching said second ROM from an OFF state to an ON state.
Claim 21
Dependent Claim
43 words
The semiconductor memory device according to claim 14, wherein said switching means is electrically connected to one of said first ROM and said second ROM based upon said switching signals supplied from a third ROM of a same type as said first ROM.
Claim 22
Dependent Claim
30 words
The semiconductor memory device according to claim 19, wherein said switching means comprises a transistor which turns on or off based on the switching signal supplied from said third ROM.
Claim 23
Dependent Claim
23 words
The semiconductor memory device according to claim 14, wherein said first ROM comprises a mask ROM and said second ROM comprises a PROM.
Claim 24
Dependent Claim
28 words
The semiconductor memory device according to claim 14, wherein said first and second ROM and said switching means forming a unit and a plurality of units are provided.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |