EP0254602A2
Expired / Lapsed
EP
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Read only memory
Assignee: Fujitsu Ltd
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Filing: 1987-05-22
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Granted: —
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Expires: 2007-05-22
Abstract
Abstract A read only memory in which portion of an address area thereof is replaced with that of another memory comprises at least one address decoding output circuit (12) with a read only memory portion (13). The address decoding output circuit (12) is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.
Inventors
- 👤 Yasushi Kasa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 10:38
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
105 words
A read only memory wherein addresses are allotted to replace a portion of an address area with at least one other memory, comprising: a read only memory portion receiving an address signal and for supplying stored data in response to a received address signal, and an address decoding output circuit receiving the address signal, for decoding the address allotted to the other memory and supplying a control signal to the other memory, and for disenabling said read only memory portion during a period that the control signal is output; said read only memory portion and said address decoding output circuit being formed to be programmable.
Claim 2
Dependent Claim
105 words
A read only memory wherein addresses are allotted to replace a portion of an address area with at least one other memory, comprising: a read only memory portion receiving an address signal and for supplying stored data in response to a received address signal, and an address decoding output circuit receiving the address signal, for decoding the address allotted to the other memory and supplying a control signal to the other memory, and for disenabling said read only memory portion during a period that the control signal is output; said read only memory portion and said address decoding output circuit being formed to be programmable.
Claim 3
Dependent Claim
40 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by connection or disconnection of transistors therein using a mask read only memory production process.
Claim 4
Dependent Claim
39 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by ion implantation of transistors therein using a mask read only memory production process.
Claim 5
Dependent Claim
44 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by forming or not forming a diffusion area in transistors therein using a mask read only memory production process.
Claim 6
Dependent Claim
45 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by positive or negative charging of a floating gate of transistors therein using a programmable read only memory production process.
Claim 7
Dependent Claim
69 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit comprises decoders which are programmable logic circuits to be programmed to one of a circuit outputting the address signal as it is, a circuit outputting the inverted address signal, and a circuit outputting a fixed level signal regardless of the address signal, and a logical gate for receiving the outputs of said decoders.
Claim 8
Dependent Claim
108 words
A read only memory as set forth in claim 6, wherein said decoder comprises a first inverter, a second inverter, a first transistor connected between the input of the first inverter and the input of the second inverter, a second transistor connected between the output of the first inverter and the input of the second inverter, and a third transistor connected between the input of the second inverter and a power source, the gates of the first, second, and third transistors being supplied with a gate input signal, and one of the first, second, and third transistors being programmed to be conductive regardless of the gate input signal.
References Cited (Backward Citations)
No citation records indexed.
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