Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method

Claim 1

In an integrated circuit memory device which includes, a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of y-lines; an address bus for addressing memory cells of the memory array, the address bus including a first bus oriented with a y-dimension and a second bus oriented with an x-dimension; an x-address generator for generating and temporarily asserting x-dimension address information; a y-address generator for generating and temporarily asserting y-dimension address information; and multiplex means for alternately operatively coupling one of the x-address generator and the y-address generator to the address bus, an improved address decoding apparatus comprising: a plurality of y-address decoders, each responsive to y-dimension address information provided on the address bus and each for producing decoded y-information to at least one of the plurality of y-lines; a plurality of separate x-address decoder means, each responsive to x-dimension address information provided on the address bus and each for producing decoded x-information for at least one of the plurality of x-lines, said decoded x-information having a first signal level on at least one of said x-lines selected by said asserted x-dimension address information and having a second signal level on all others of said plurality of x-lines; and a plurality of separate means, each operatively coupled to at least one of said plurality of x-address decoder means, for sustaining, after said x-address generator stops temporarily asserting said x-dimension address information, said first signal level on said at least one x-line and said second signal level on said other x-lines.