Intermediary wheel slip sequence speed processing system for multiple axle railway vehicles

Claim 2

A wheel slip sequence speed processing system for multiple axle railway vehicles comprising, first means for determining whether all the axles on the vehicle are slipping at the same time, second means for selecting the maximum axle speed value on the vehicle, third means for selecting the minimum acceleration axle rate value on the vehicle, fourth means for converting and increasing the bit size of the highest axle speed value, fifth means for processing the converted bit size highest axle speed value when all the axles are not slipping and for determining an average deceleration rate to establish a reference axle speed value when all of the axles are slipping, and sixth means for reconverting the bit size of the highest and reference axle speed values.

Claim 3

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 1, wherein said fourth means converts an 8-bit number to a 16-bit number.

Claim 4

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 2 wherein said sixth means reconverts the 16-bit number to an 8-bit number.

Claim 5

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 1, wherein said first means is a logic network.

Claim 6

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 4, wherein said logic network includes a plurality of OR gate circuits.

Claim 7

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 5, wherein each of said plurality of OR gate circuits includes two inputs.

Claim 8

The wheel slip sequence speed processing system for multiple railway vehicles as defined in claim 4, wherein said logic network includes a plurality of AND gate circuits.

Claim 9

The wheel slip sequence sped processing system for multiple axle railway vehicles as defined in claim 7, wherein each of said plurality of AND gate circuits includes two inputs.

Claim 10

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 4, wherein said logic network includes a plurality of stages.

Claim 11

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 9, wherein a second stage of said plurality of stages includes a pair of AND gates.

Claim 12

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 9, wherein a third stage of said plurality of stages includes an AND gate.

Claim 13

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 9, wherein a first stage of said plurality of stages includes four OR gates.

Claim 14

The wheel slip sequence slip processing system for multiple axle railway vehicles as defined in claim 12, wherein each of said four OR gates includes one input connected to a primary wheel slip condition terminal of one of four wheels of the railway vehicle and includes another input connected to a synchronous wheel slip condition terminal of said one of the four wheels of the railway vehicle.

Claim 15

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 12, wherein the outputs of a first pair of said four OR gates are connected to the inputs of a first two-input AND gate and the output of a second pair of said OR gates are connected to the inputs of a second two-input AND gate.

Claim 16

The wheel slip sequence speed processing system for multiple axle railway vehicles as defined in claim 14, wherein the outputs of said first and said second two-input AND gates are connected to the respective inputs of a two-input AND gate.

Claim 17

A wheel slip control system for a multiple-axle vehicle comprising, a logic network including a plurality of two (2) input OR gates in which one input is supplied with primary slip indication signals on a given axle and the other input is supplied with synchronous slip indication signals on the given axle, a pair of two-input AND gates conditioned by said plurality of OR gates and a single two-input AND gate conditioned by said pair of AND gates to determine if all the axles are slipping at the same time, a maximum axle speed selection comparator for selecting the maximum speed value, a highest axle speed converter for increasing the bits of the selected maximum speed value, a speed differential calculator for calculating the difference between the present increased bit speed value and the previous increased bit speed value, a minimum axle rate selection comparator for selecting the minimum axle rate, a rate constant determination circuit for selecting a constant value in response to the minimum axle rate, a difference summation circuit for summing each speed difference calculation over a given period of time and for subtracting the minimum axle rate constant value from the summation of the speed difference calculation, an average speed summation circuit for dividing the speed difference summation value by a given number of time periods, a difference hold circuit for holding the average speed difference value at the beginning of a sequence in which all the axles are slipping, an interslip speed sequence circuit for determining the increased bit speed value when at least one axle is not slipping and for determining a speed reference value by subtracting the average speed difference from the previous calculated speed reference value, and a vehicle speed reconverter for reducing the bits of the output received from interslip speed sequence circuit.

Claim 18

A wheel slip control system for a multiple-axle vehicle comprising, a logic network including a plurality of two (2) input OR gates in which one input is supplied with primary slip indication signals on a given axle and the other input is supplied with synchronous slip indication signals on the given axle, a pair of two-input AND gates conditioned by said plurality of OR gates and a single two-input AND gate conditioned by said pair of AND gates to determine if all the axles are slipping at the same time, a maximum axle speed selection comparator for selecting the maximum speed value, a highest axle speed converter for increasing the bits of the selected maximum speed value, a speed differential calculator for calculating the difference between the present increased bit speed value and the previous increased bit speed value, a minimum axle rate selection comparator for selecting the minimum axle rate, a rate constant determination circuit for selecting a constant value in response to the minimum axle rate, a difference summation circuit for summing each speed difference calculation over a given period of time and for subtracting the minimum axle rate constant value from the summation of the speed difference calculation, an average speed summation circuit for dividing the speed difference summation value by a given number of time periods, a difference hold circuit for holding the average speed difference value at the beginning of a sequence in which all the axles are slipping, an interslip speed sequence circuit for determining the increased bit speed value when at least one axle is not slipping and for determining a speed reference value by subtracting the average speed difference from the previous calculated speed reference value, and a vehicle speed reconverter for reducing the bits of the output received from interslip speed sequence circuit.