US5243558A
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Dynamic random access memory device with bit lines partially shared between sense amplifier circuits
Assignee: NEC Electronics Corp
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Filing: 1992-02-25
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Granted: 1993-09-07
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Expires: 2012-02-25
Abstract
Abstract A dynamic random access memory device in the folded bit line configuration comprises first sense amplifier circuits located on one side of sets of bit lines associated with first transfer units, second sense amplifier circuits located on the other side of the sets of bit lines asoicated with second transfer units, and sets of word lines, and each sets of bit lines and each set of word lines respectively consist of first to third bit lines and first to third word lines for providing nine addressable locations, wherein memory cells are provided at six addressable locations selected from the nine addressable locations, and each set of bit lines respectively propagate two data bits read out from two of the six memory cells to the first and second sense amplifier circuits, thereby increasing the number of memory cells in a unit area.
Inventors
- 👤 Takanori Saeki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
306 words
A dynamic random access memory device fabricated on a single semiconductor chip, comprises: a) a memory cell array implemented by a plurality of memory cells respectively storing data bits; b) a plurality of sets of bit lines associated with said memory cell array, and each of said sets of bit lines having first, second and third bit lines; c) a plurality of word lines providing a plurality of addressable locations at virtual crossing points together with said first, second and third bit lines of said sets of bit lines, said plurality of memory cells being selectively assigned to said plurality of addressable locations, one of said plurality of word lines allowing two of said first, second and third bit lines of each set to propagate two data bits read out from said memory cell array; d) first sense amplifier circuits provided on one side of said sets of bit lines, and respectively associated with said sets of bit lines; e) first transfer gate units respectively coupled between said sets of bit lines and said first sense amplifier circuits; f) second sense amplifier circuits provided on the other side of said sets of bit lines, and respectively associated with said sets of bit lines; g) second transfer gate units respectively coupled between said sets of bit lines and said second sense amplifier circuits; and h) a controlling unit operative to control said first and second transfer gate units in such a manner that one of said first, second and third bit lines of each set supplies a reference voltage level to the associated first and second sense amplifier circuits for discriminating logic levels of said two data bits read out from memory cells selected by one of said word lines to the others of said first, second and third bit lines in the form of voltage level.
Claim 2
Dependent Claim
306 words
A dynamic random access memory device fabricated on a single semiconductor chip, comprises: a) a memory cell array implemented by a plurality of memory cells respectively storing data bits; b) a plurality of sets of bit lines associated with said memory cell array, and each of said sets of bit lines having first, second and third bit lines; c) a plurality of word lines providing a plurality of addressable locations at virtual crossing points together with said first, second and third bit lines of said sets of bit lines, said plurality of memory cells being selectively assigned to said plurality of addressable locations, one of said plurality of word lines allowing two of said first, second and third bit lines of each set to propagate two data bits read out from said memory cell array; d) first sense amplifier circuits provided on one side of said sets of bit lines, and respectively associated with said sets of bit lines; e) first transfer gate units respectively coupled between said sets of bit lines and said first sense amplifier circuits; f) second sense amplifier circuits provided on the other side of said sets of bit lines, and respectively associated with said sets of bit lines; g) second transfer gate units respectively coupled between said sets of bit lines and said second sense amplifier circuits; and h) a controlling unit operative to control said first and second transfer gate units in such a manner that one of said first, second and third bit lines of each set supplies a reference voltage level to the associated first and second sense amplifier circuits for discriminating logic levels of said two data bits read out from memory cells selected by one of said word lines to the others of said first, second and third bit lines in the form of voltage level.
Claim 3
Dependent Claim
88 words
A dynamic random access memory device as set forth in claim 1, in which said plurality of word lines are broken down into sets of word lines each having first, second and third word lines, said first, second and third bit lines of each set of bit lines and said first, second and third word lines of each set of word lines providing nine virtual crossing points, six virtual crossing points selected from said nine virtual crossing points being occupied by memory cells of said memory cell array.
Claim 4
Dependent Claim
72 words
A dynamic random access memory device as set forth in claim 2, in which virtual crossing points of said first word line and said second and third bit lines, virtual crossing points of said second word line and said first and third bit lines and virtual crossing points of said third word line and said first and second bit lines are occupied by said six memory cells of said memory cell array.
Claim 5
Dependent Claim
70 words
A dynamic random access memory device as set forth in claim 3, in which each of said first transfer gate units is implemented by first, second and third transfer transistors, said first transfer transistor being coupled with one of two input nodes of the associated first sense amplifier circuit, said second and third transfer transistors being commonly coupled with the other input node of said associated first sense amplifier circuit.
Claim 6
Dependent Claim
70 words
A dynamic random access memory device as set forth in claim 4, in which each of said second transfer gate units is implemented by fourth, fifth and sixth transfer transistors, said fourth and fifth transfer transistors being commonly coupled with one of two input nodes of the associated second sense amplifier circuit, said sixth transfer transistor being coupled with the other input node of said associated second sense amplifier circuit.
Claim 7
Dependent Claim
79 words
A dynamic random access memory device as set forth in claim 5, in which said controlling unit is coupled through first, second, third, fourth, fifth and sixth control signal lines respectively coupled with gate electrodes of said first to sixth transfer transistors, said first to sixth control signal lines allowing said first bit line to be shared between the associated first and second sense amplifier circuits for supplying said reference voltage level when said first word line is selected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-06 | 1997-03-08 | 1997-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-06 | 2001-03-08 | 2001-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-06 | 2005-03-08 | 2005-09-07 | $7700.00 | Window Closed / Lapsed |